LTC4316 Datasheet by Analog Devices Inc.

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LTC4316
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For more information www.linear.com/LTC4316
TYPICAL APPLICATION
FEATURES DESCRIPTION
Single I2C/SMBus
Address Translator
The LT C
®
4316 enables the hardwired address of one or
more I2C or SMBus slave devices to be translated to a
different address. This allows slaves with the same hard-
wired address to coexist on the same bus. Only discrete
resistors are needed to select the new address and no
software programming is required. Up to 127 different
address translations are available.
The LTC4316 incorporates a pass-through mode which
disables the address translation and allows general call
addressing by the master. The LTC4316 is designed to
automatically recover from abnormal bus conditions like
bus stuck low or premature STOP bits.
PART NUMBER
NUMBER OF INPUT
CHANNELS
NUMBER OF OUTPUT
CHANNELS
LTC4316 1 1
LTC4317 1 2
LTC4318 2 2
APPLICATIONS
n Allows Multiple Slaves with the Same Address to
Coexist on the Same Bus
n Resistor Configurable Address Translation
n No Software Programming Required
n Compatible with SMBus, I2C and I2C Fast Mode
n Pass-Through Mode Allows General Call Addressing
n ±4kV HBM ESD Ruggedness
n Level Translation for 2.5V, 3.3V and 5V Buses
n Stuck Bus Timeout
n Prevents SDA and SCL Corruption During Live Board
Insertion and Removal
n Support Bus Hot Swap
n 10-Lead MSOP and DFN 3mm × 3mm Packages
n I2C, SMBus Address Expansion
n Address Translation
n Servers
n Telecom
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286. Patent pending.
SCL
SDA
4316 TA01a
3.3V
976k 182k
3.3V
3.3V
MASTER
SCLOUT
SDAOUT
READY
SCLIN
SDAIN
ENABLE
SENDS
ADDRESS 0x34
SCL
SDA
5V
SLAVE
RECEIVES
ADDRESS 0x36
TRANSLATES BY 0x02
GNDXORHXORL
LTC4316
VCC
4316 TA01b
TRANSLATION
BYTE
SDAOUT
SCLIN
SDAIN
ADDRESS BITS
START
BIT
a6 a5 a4 a3 a2 a1 a0
0 1 1 0 1 0 0 = 0x34
0 0 0 0 0 1 0 = 0x02
0
0
0
0 1 1 0 1 1 0 = 0x36
R/W
BIT
ACK
BIT
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LTC4316
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ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage VCC ............................. 0.3V to 6V
Input Voltages
ENABLE ........................................................ 0.3V to 6V
XORL, XORH ....................................0.3V to VCC + 0.3V
Output Voltage
READY ......................................................... 0.3V to 6V
Output Currents
READY, SDAOUT ....................................................50mA
(Notes 1, 2)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4316CDD#PBF LTC4316CDD#TRPBF LGSW 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC4316IDD#PBF LTC4316IDD#TRPBF LGSW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4316CMS#PBF LTC4316CMS#TRPBF LTGSV 10-Lead Plastic MSOP 0°C to 70°C
LTC4316IMS#PBF LTC4316IMS#TRPBF LTGSV 10-Lead Plastic MSOP –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some Packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Input/Output Voltages
SCLIN, SCLOUT, SDAIN, SDAOUT ................ 0.3V to 6V
Operating Temperature Range
LTC4316C ................................................ C to 70°C
LTC4316I .............................................40°C to 8C
Storage Temperature Range .................. 6C to 150°C
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
11
GND
9
6
7
8
4
5
3
2
1SCLIN
SCLOUT
SDAOUT
SDAIN
READY
GND
XORH
XORL
VCC
ENABLE
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, PCB CONNECTION OPTIONAL
1
2
3
4
5
GND
XORH
XORL
VCC
ENABLE
10
9
8
7
6
SCLIN
SCLOUT
SDAOUT
SDAIN
READY
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 160°C/W
PIN CONFIGURATION
LTC43 1 6 L7 LJUW 3
LTC4316
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply
VCC Input Supply Range l2.25 5.5 V
ICC Input Supply Current ENABLE = 3.3V, SCLIN = SDAIN = 0V l0.6 2 mA
ENABLE = 0V, SCLIN = SDAIN = 0V l350 800 μA
VCC(UVLO) VCC Supply Undervoltage Lockout VCC Rising l1.9 2.1 2.2 V
VCC(HYST) VCC Supply Undervoltage Lockout Hysteresis 100 mV
ENABLE and READY
VENABLE(TH) ENABLE Threshold Voltage ENABLE Rising l1 1.4 1.8 V
VENABLE(HYST) ENABLE Hysteresis 50 mV
IENABLE(LEAK) ENABLE Input Current l±1 μA
VREADY(OL) READY Output Low Voltage I = 3mA l0.4 V
IREADY(OH) READY Off Leakage Current VCC = VREADY = 5.5V l±5 μA
SCLIN, SDAIN, SCLOUT, SDAOUT
VSCL,SDA(TH) Threshold Voltage SDA, SCL Pins Rising l1.5 1.8 2.0 V
VSCL,SDA(HYST) Hysteresis 50 mV
ISCL,SDA(LEAK) Leakage Current SDA, SCL Pins = 5.5V, 0V, VCC = 5.5V, 0Vl±10 μA
ISCL,SDA(LEAK-INOUT)Input to Output Leakage Current SDAIN, SCLIN Pins = 5.5V, VCC = 5.5V,
SDAOUT, SCLOUT Pins = 4.5V
l±10 μA
CSCL,SDA Pin Capacitance Note 3 l10 pF
VSCL,SDA(PRE) Precharge Voltage l0.8 1 1.2 V
VSDAOUT(OL) SDAOUT Output Low Voltage I = 4mA l0.4 V
RDS(ON) Pass Switch On Resistance VCC = 2.25V, SCLIN = SDAIN = 0.4V
VCC = 3.3V, SCLIN = SDAIN = 0.4V
VCC = 5V, SCLIN = SDAIN = 0.4V
l
l
l
3
2.2
1.8
12
8
6
Ω
Ω
Ω
XORH, XORL
IXORH/XORL XORH and XORL Input Current l±100 nA
I2C Interface Timing
fSCL(MAX) Maximum SCLIN Clock Frequency Note 3 l400 kHz
tPDHL(SDAOUT) SDAOUT Fall Delay C = 100pF, RPULLUP = 10k l170 300 ns
tf(SDAOUT) SDAOUT Fall Time C = 100pF, RPULLUP = 10k l20 60 300 ns
tTIMEOUT Stuck Bus Timeout SCLIN Held Low or High l25 30 35 ms
tIDLE Bus Idle Time l80 120 160 μs
tGLITCH SCLIN and SDAIN Glitch Filter l50 100 ns
Note 2: All currents into pins are positive and all voltages are referenced to
GND unless otherwise indicated.
Note 3: Guaranteed by design and not tested.
LTC4316 as (mm Hg) R Baa m /-»—--“’/’ // i ’——- 4 I” " I—T'” vcg=225v ‘ , / um “45°C 225v E zazv / / / &/ > 1 ms) t 24m
LTC4316
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TYPICAL PERFORMANCE CHARACTERISTICS
TIMING DIAGRAM
Pass Switch On Resistance vs
Temperature
READY Output Low
Voltage vs Current
SDAOUT Fall Delay vs
Temperature
Supply Current vs Temperature
Standby Supply Current vs
Temperature Pass Switch On Resistance vs VCC
TA = 25°C, VCC = 3.3V unless otherwise noted.
4316 EC
SDAOUT
SDAIN 50%
tPDHL(SDAOUT)
t
f(SDAOUT)
70%
50%
30%
TEMPERATURE (°C)
–50
CC
0.7
0.6
0.5
0.4 0 50–25 25 75
ENABLE = VCC
VCC = 2.25V
VCC = 5V
VCC = 3.3V
TEMPERATURE (°C)
–50
I
CC
(µA)
800
700
500
300
600
400
200
100
00 50–25 25 75
4316 G02
100
ENABLE = 0V
VCC (V)
2.0
R
DS(ON)
(Ω)
6
5
3
1
4
2
03.0 4.02.5 3.5 4.5
4316 G03
5.0
TA = –40°C
TA = 85°C
TA = 25°C
SDAIN = SCLIN = 0.4V
TEMPERATURE (°C)
–50
R
DS(ON)
(Ω)
6
5
3
1
4
2
00 50–25 25 75
4316 G04
100
VCC = 5V
VCC = 2.25V
VCC = 3.3V
SDAIN = SCLIN = 0.4V
IREADY (mA)
0
V
READY(OL)
(mV)
100
80
40
60
20
02 64 8
4316 G05
10
TA = –40°C
TA = 85°C
VCC = 3.3V
TA = 25°C
TEMPERATURE (°C)
–50
t
PDHL(SDAOUT)
(ns)
240
220
200
180
160
120
140
100 0 50–25 25 75
4316 G06
100
VCC = 3.3V
C = 100pF
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LTC4316
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TYPICAL PERFORMANCE CHARACTERISTICS
SDAOUT Fall Delay vs Bus
Capacitance
SDAOUT Fall Time vs
Temperature
SDAOUT Fall Time vs Bus
Capacitance
TA = 25°C, VCC = 3.3V unless otherwise noted.
PIN FUNCTIONS
XORL: Translator XOR Lower Nibble Configuration Input.
The DC voltage at this pin configures the lower 4-bit nibble
of the address translation byte. Tie the pin to an external
resistive divider connected between VCC and GND to set
the desired DC voltage.
XORH: Translator XOR Upper Nibble Configuration Input.
The DC voltage at this pin configures the upper 3-bit nibble
of the address translation byte. Tie the pin to an external
resistive divider connected between VCC and GND to set
the desired DC voltage. Connect this pin to VCC to activate
pass-through mode. See Application Information section
for more details.
ENABLE: Enable Input. If ENABLE pin is low, the address
translation is disabled, SDAIN is disconnected from SD-
AOUT, and SCLIN is disconnected from SCLOUT. A low
to high transition on ENABLE restarts the configuration of
the address translation byte and also enables the address
translation. Connect to VCC if unused.
Exposed Pad (DFN Package Only): Exposed pad may be
left open or connected to device GND.
GND: Device Ground.
READY: Ready Status Output. This is an open drain output
to indicate that the device is ready for address translation.
The pin releases high when the LTC4316 has completed
configuration of the address translation byte, SDAIN is
connected to SDAOUT and SCLIN is connected to SCLOUT.
Connect a pull-up resistor, typically 10k, from this pin to
the bus pull-up supply. Leave open or tie to GND if unused.
SCLIN: Input Bus Clock Input and Output. Connect this
pin to the SCL line on the master side. An external pull-up
resistor or current source is required.
SCLOUT: Output Bus Clock Input and Output. Connect this
pin to the SCL line on the slave side. An external pull-up
resistor or current source is required.
SDAIN: Input Bus Data Input and Output. Connect this pin
to the SDA line on the master side. An external pull-up
resistor or current source is required.
SDAOUT: Output Bus Data Input and Output. Connect this
pin to the SDA line on the slave side. An external pull-up
resistor or current source is required.
VCC: Power Supply Input (2.25V to 5.5V). If the supply
voltages for the input and output buses are different, con-
nect this pin to the lower supply. If the input and output
supplies have the same nominal value and with tolerance
less than or equal to ±10%, connect VCC to either supply.
Bypass with at least 0.1μF to GND.
CBUS (pF)
0
t
PDHL(SDAOUT)
(ns)
300
100
125
150
175
200
225
250
275
200 600400 800
4316 G07
1000
VCC = 5V
VCC = 2.25V
VCC = 3.3V
TEMPERATURE (°C)
–50
t
f(SDAOUT)
(ns)
120
100
60
80
40
20 0 50–25 25 75
4316 G08
100
C = 100pF
VCC = 5V
VCC = 2.25V
VCC = 3.3V
CBUS (pF)
0
t
f(SDAOUT)
(ns)
120
100
60
80
40
20 200 600400 800
4316 G09
1000
VCC = 5V
VCC = 2.25V
VCC = 3.3V
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LTC4316
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BLOCK DIAGRAM
OPERATION
The LTC4316 is an I2C/SMBus address translator. It bridges
two segments of an I2C bus, reading incoming addresses
on the master side and retransmitting them to the slave
side with the 7-bit I2C addresses translated in real time.
This allows multiple I2C devices with the same address
to be connected to the same bus without interference.
4316 BD
I2C HOT
SWAP
LOGIC
7-BIT
ADDRESS
TRANSLATION
BYTE
GND
CONTROL
LOGIC
VCC/2
CMP6 CMP5
PRECHARGE 1.4V
N4
1V
200k
PRECHARGE
1V
READY
SDAOUT
SCLOUT
XORL
XORH
SDAIN
SCLIN
VCC
+
N3
+
CMP3
1.8V
+
1.8V
CMP1
+
I2C HOT
SWAP
LOGIC
CMP4
1.8V
+
GLITCH
FILTER
1.8V
CMP2
+
GLITCH
FILTER
XOR
N1
N2
200k
PRECHARGE PRECHARGEPRECHARGE
1V
200k
1V
200k
ENABLE
The translated addresses are configured with external
resistors, and no extra software is required. An ENABLE
pin allows bus segments to be enabled and disabled, and
the LTC4316 allows hot swapping isolated bus segments
together.
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LTC4316
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OPERATION
SDAOUT pin. Once all 7 bits of the address are processed,
the LTC4316 turns on N2 again to reconnect SDAIN to
SDAOUT. The master then transmits the R/W bit directly
to the slave. If the new, translated address on SDAOUT
matches the slave’s address, the slave pulls SDAOUT low
to acknowledge (ACK bit). N2 remains on and the rest of
the data bytes are transmitted unmodified between the
master and slave. The address translation process restarts
when the master issues a new START bit.
Figure 2 shows typical waveforms for the circuit on the
front page. In this example, the master transmits address
0x34 while the slave is configured to respond to address
0x36. The resistive dividers at the XORL and XORH pins are
configured to generate an address translation byte of 0x02.
Note that in this example, the 8-bit hexadecimal address
format (with R/W=0) is used. 7-bit addresses are also
commonly found in I2C device documentation. Make sure
to use the correct format when calculating the address
translation byte. Table 1 shows examples of both formats.
Figure 1. Basic Functions of the LTC4316
4316 F01
V
CC1
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
V
CC2
SLAVE
#1
LTC4316
SLAVE
#2
7-BIT ADDRESS TRANSLATION
BYTE SHIFT REGISTER
0000010 ENABLE
ADDRESS
TRANSLATION
N3
1.8V
CMP2
+
XOR
N1
N2
Figure 1 shows an I2C master connected to the input bus
of the LTC4316 (SCLIN and SDAIN). The slave devices
requiring address translation are connected to the output
bus of the LTC4316 (SCLOUT and SDAOUT). Any other
slave devices that do not require address translation are
placed together with the master on the input bus of the
LTC4316. Tw o switches (N1 and N2) inside the LTC4316
connect the input bus to the output bus. N1 connects
SCLIN to SCLOUT while N2 connects SDAIN to SDAOUT.
In most conditions, N1 and N2 stay on so that the input
and output buses are connected.
Translation starts when the master issues a START bit
(SDAIN goes low while SCLIN is high). The LTC4316
turns off N2 to disconnect SDAIN from SDAOUT. As the
master sends the address byte, the LTC4316 translates
the incoming address at the SDAIN pin to a new address
at the SDAOUT pin by XORing each incoming bit with
a user-configurable translation byte, one bit at a time.
N3 turns on and off to send out the new address to the
Figure 2. Basic Address Translation Waveforms
TRANSLATION
BYTE
SDAOUT
SCLIN
SDAIN
ADDRESS BITSSTART
a6 a5 a4 a3 a2 a1 a0
0110100
0000010
0
0
0
0 110110
= 0x34
= 0x02
= 0x36
4316 F02
N2 GATE N2 ON N2 ON N2 OFF
R/W
BIT
ACK
BIT
LTC4316 HARD 0x34 L7LJCUEN2
LTC4316
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OPERATION
Figure 4. Tw o Slaves Sharing One LTC4316Figure 3. Tw o Independent Address Translation
Setting the Translation Byte
When the LTC4316 is first powered up or any time a rising
edge is detected on the ENABLE pin, the LTC4316 reads
the voltages at XORH and XORL pins to determine the
7-bit translation byte. These voltages are referenced to
VCC so a resistive divider at each of these pins is the most
convenient way to set the voltages. The required transla-
tion byte can be determined by taking the bitwise XOR of
the slave’s original address and the desired input address.
The voltages at the XORH and XORL pins configure the
translation byte. The XORL voltage configures the lower
4 translation bits (excluding the R/W bit), while the XORH
voltage configures the upper 3 translation bits. Tables 2
and 3 show the recommended resistive divider values. RLT
and RLB are the top and bottom resistors connected to
XORL, while RHT and RHB are the top and bottom resistors
connected to XORH (Figure 5). Use 1% tolerance resistors
for RLT , RLB, RHT and RHB.
SCL
SDA
4316 F03
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
SLAVE #1
INPUT ADDRESS 0x32
TRANSLATION BYTE 0x06
SCL
SDA
SLAVE
#1
HARDWIRED ADDRESS
0x34
LTC4316
#1
SCLOUT
SDAOUT
SCLIN
SDAIN
SLAVE #3
INPUT ADDRESS 0x36
TRANSLATION BYTE 0x02
SCL
SDA
SLAVE
#3
HARDWIRED ADDRESS
0x34
LTC4316
#2
SCL
SDA
SLAVE
#2
HARDWIRED ADDRESS
0x34
00110010
00000110
00110100
00110110
00000010
00110100
SCL
SDA
4316 F04
MASTER
SCL
SDA
SLAVE
#2
HARDWIRED ADDRESS
0x34
SCLOUT
SDAOUT
SCLIN
SDAIN
TRANSLATION BYTE
0x02
SLAVE #1
INPUT ADDRESS
0x36
SLAVE #3
INPUT ADDRESS
0x32
SCL
SDA
SLAVE
#1
HARDWIRED ADDRESS
0x34
LTC4316
SCL
SDA
SLAVE
#3
HARDWIRED ADDRESS
0x30
00110110
00000010
00110100
00110010
00000010
00110000
System Configurations
There are several ways that individual slaves or banks of
slaves can be connected to an LTC4316. In Figure 3, each
slave is paired with an LTC4316. This configuration allows
for maximum flexibility in allocating the bus addresses.
Both read and write operations and all protocols supported
by the LTC4316 are allowed. Figure 4 shows two slaves
with different hardwired addresses translated to two dif-
ferent addresses using a single LTC4316 and a common
translation byte. A program is available to help the user
visualize an I2C bus with the LTC4316; this program can
be found in the following link:
www.linear.com/TranslatorTool
Table 1.
DESCRIPTION BINARY ADDRESS 7-BIT HEX ADDRESS
WITHOUT R/W
8-BIT HEX ADDRESS
WITH R/W=0
a6 a5 a4 a3 a2 a1 a0 R/W
Input Address from SDAIN 0 0 1 1 0 1 0 0 0x1A 0x34
Translation Byte 0 0 0 0 0 0 1 0 0x01 0x02
Output Address to SDAOUT 0 0 1 1 0 1 1 0 0x1B 0x36
LTC43 1 6 L7 LJUW 9
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OPERATION
For example, if RLT = 976k, RLB = 102k, RHT = 1000k, and
RHB = 280k, the lower 4 translation bits are 0001b and
the upper 3 bits are 011b. The 8-bit hexadecimal address
translation byte is obtained by adding a 0 as the LSB, which
gives 0110 0010b or 0x62. If the configuration voltages
at XORL and XORH pins are the same, they can be tied
together and connected to a single resistive divider. Alter-
First choose a total resistance value RTOTAL
RA3 = RTOTAL • (VXORH/VCC)
RA2 = (RTOTAL • VXORL/VCC) – RA3
RA1 = RTOTAL – RA3 – RA2
Use 1% tolerance resistors for RA1, RA2 and RA3.
Once the XORL and XORH pins are read, the LTC4316
turns on switches N1 and N2, connecting the input and
output, and the READY pin goes high to indicate that the
LTC4316 is ready to start address translation.
The address translation byte can be changed during
operation by changing the XORH and XORL voltages and
toggling the ENABLE pin (high-low-high). This triggers
the LTC4316 to re-read the XORL and XORH voltages.
Enable/UVLO
If the ENABLE pin is driven below VENABLE(TH) or if VCC
is below the UVLO threshold, the LTC4316 shuts down.
The internal shift register storing the address translation
byte is cleared, address translation is disabled, switches
Table 2. Setting the Resistive Divider at XORL
LOWER
4-BIT OF
TRANSLATION
BYTE
VXORL/VCC
RECOMMENDED
RLT [kΩ]
RECOMMENDED
RLB [kΩ]
a3 a2 a1 a0
0 0 0 0 ≤ 0.03125 Open Short
0 0 0 1 0.09375 ±0.015 976 102
0 0 1 0 0.15625 ±0.015 976 182
0 0 1 1 0.21875 ±0.015 1000 280
0 1 0 0 0.28125 ±0.015 1000 392
0 1 0 1 0.34375 ±0.015 1000 523
0 1 1 0 0.40625 ±0.015 1000 681
0 1 1 1 0.46875 ±0.015 1000 887
1 0 0 0 0.53125 ±0.015 887 1000
1 0 0 1 0.59375 ±0.015 681 1000
1 0 1 0 0.65625 ±0.015 523 1000
1 0 1 1 0.71875 ±0.015 392 1000
1 1 0 0 0.78125 ±0.015 280 1000
1 1 0 1 0.84375 ±0.015 182 976
1 1 1 0 0.90625 ±0.015 102 976
1 1 1 1 ≥ 0.96875 Short Open
Table 3. Setting the Resistive Divider at XORH
UPPER
3-BIT OF
TRANSLATION
BYTE
VXORH/VCC
RECOMMENDED
RHT [kΩ]
RECOMMENDED
RHB [kΩ]
a6 a5 a4
0 0 0 ≤ 0.03125 Open Short
0 0 1 0.09375 ±0.015 976 102
0 1 0 0.15625 ±0.015 976 182
0 1 1 0.21875 ±0.015 1000 280
1 0 0 0.28125 ±0.015 1000 392
1 0 1 0.34375 ±0.015 1000 523
1 1 0 0.40625 ±0.015 1000 681
1 1 1 0.46875 ±0.015 1000 887
Figure 5. Address Translation Byte Configuration Resistors
Figure 6. Address Translation Byte Configuration Using
Three Resistors
4316 F05
V
CC
RHT RLT
XORLXORH
LTC4316
VCC
RHB RLB
4316 F06
V
CC
RA1
XORH
LTC4316
VCC
XORL
RA3
RA2
natively, three resistors can be used to configure the XORL
and XORH pins (Figure 6). Use the following procedure
to calculate the value of the three resistors:
LTC4316 ADDRESS Ems J_|_|_|_|_|_|_| _|—|_|—| _|—|_ _|'|_l_L|_| 7 1 T T W? T ‘IO
LTC4316
10
4316fa
For more information www.linear.com/LTC4316
OPERATION
N1, N2 and N3 are off, the READY pin is pulled low and
the quiescent current drops to 350μA.
Precharge and Hot Swap
When the LTC4316 is first powered on, switches N1 and
N2 are initially off. This allows a LTC4316 and its con-
nected slaves to be hot swapped onto an active I2C bus.
Internal precharge circuitry initially sets the bus lines to
1V through a 200k resistor, minimizing disturbance to an
active bus when the LTC4316 is connected. The LTC4316
keeps N1 and N2 off until ENABLE goes high, the XORL/
XORH pins are read, and both sides of the I2C bus are
idle (indicated either by a STOP bit or all bus pins high for
longer than 120μs). Once these conditions are met, N1
and N2 turn on, and the READY pin goes high to indicate
that the LTC4316 is ready to start address translation.
Pass-Through Mode
If the master wants to communicate with the slave us-
ing the general call address, it can temporarily disable
address translation by pulling XORH high. This disables
address translation and keeps N1 and N2 on regardless
of the activity on the buses. Any translation that may be in
progress is stopped immediately when XORH goes high.
Extra Transitions on SDAOUT
In an I2C /SMBus system, the master changes the state of
the SDA line when SCL is low. The LTC4316 also advances
the address translation byte shift register when the SCLIN
is low. The translation byte transitions occur approximately
100ns after the falling edge of SCLIN. If the SDAIN tran-
sitions sent by the master do not coincide exactly with
the LTC4316 address translation bit transitions, an extra
transition on SDAOUT may appear (Figure 7). These extra
SDA transitions are like glitches similar to those occurring
during normal Acknowledge bit transitions and do not pose
problems in the system because devices on the bus latch
SDA data only when SCL is high.
Level Translation and Supply Voltage Matching
The LTC4316 can operate with different supply voltages
on the input and output bus, and it will level shift the
voltages on the SCLIN, SDAIN, SCLOUT, and SDAOUT
pins to match the supply voltage at each side. VCC must
be powered from the lower of the two supply voltages
for level shifting to operate correctly. For example, if the
input bus is powered by a 5V supply and the output bus
is powered by a 3.3V supply, the LTC4316 VCC pin must
be connected to the 3.3V supply as shown in Figure 8.
Figure 7. Extra Transitions on SDAOUT While SCL Is Low
TRANSLATION BYTE
SDAOUT
SCLIN
SDAIN
GLITCH
0101
0110
0011
4316 F07
N2 GATE N2 OFF
ADDRESS BITS
GLITCH
Figure 8. A 5V to 3.3V Level Translation Application
4316 F08
5V
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
3.3V
SLAVE
#1
LTC4316
VCC
If the LTC4316 supply pin is connected to the higher bus
supply, current may flow through the switches N1 and
N2 to the bus with lower supply. If the voltage difference
is less than 1V, this current is limited to less than 10μA.
This allows the input and output buses to be connected
to nominally identical supplies that may have up ±10%
tolerance, and the LTC4316 VCC pin can be connected to
either supply.
Extra START and STOP Bits
During normal operation, an I2C master should not issue
a START or STOP bit within a data byte. I2C slave behavior
when such a command is received can be unpredictable.
The LTC4316 will recover automatically when an unex-
pected START or STOP is received during the address byte;
however, depending on the state of the translating bits,
L7 LJUW ADDRESS BIT LTC43 1 6 11
LTC4316
11
4316fa
For more information www.linear.com/LTC4316
OPERATION
it may convert START bits to STOP bits and vice versa,
causing unexpected slave behavior.
If an START bit is received during the address byte when
the active translating bit is a 1, the slave device will see
a STOP bit. This will typically reset the slave and cause it
to miss the remainder of the transmission. If the START
bit is received while the active translating bit is a 0, the
START passes through the LTC4316 unchanged. The slave
will react in the same way it would if the LTC4316 was
not present, and will typically reset when the master next
issues a STOP bit. In both cases, the LTC4316 automati-
cally resets at the next STOP bit and the next message
will be transmitted normally.
If an STOP bit is received during the address byte, the
LTC4316 will abort the address translation and ensure
that a STOP bit is issued at SDAOUT to reset the slave. If
the active translating bit is a 0 when the STOP arrives, it is
not modified, and the slave will see the STOP and typically
reset. If the active translating bit is a 1 when the STOP
arrives, the slave device will see a START bit. This might
leave the slave in an indeterminate state, so the LTC4316
briefly disconnects the slave from the master, adds a short
delay, and then generates a STOP bit at the SDAOUT pin
(Figure 9). It then reconnects the busses and waits for a
START bit to begin the next transmission. Again, in both
cases, the LTC4316 automatically resets and the next
message will be transmitted normally.
Stuck Bus Timeout
During the address translation, if SCLIN stays low or high
for more than 30ms without any transitions, the LTC4316
will abort the address translation and reconnect SDAIN to
SDAOUT. It will then wait for a START bit to start a new
address translation. This prevents any bus stuck low/
high conditions from permanently disconnecting SDAIN
from SDAOUT.
Supported Protocols
The LTC4316 is designed to support most I2C and SMBus
message protocols. The only exceptions are protocols that
use pre-assigned addresses on the slave side of the bus.
Supported I2C and SMBus Protocols
Send/Receive Byte
Write Byte/Word
Read Byte/Word
Process Call
Block Write/Read
Block Write-Block Read Process Call
Extended Read and Write Commands
General Call (I2C only)
Start Byte (I2C only)
PMBus (without PEC)
Unsupported I2C Protocols
• 10-Bit Addressing
Device ID
Ultra Fast-Mode I2C Bus Protocol
Unsupported SMBus Protocols
SMBus Host Notify
Address Resolution Protocol (ARP)
Parity Error Code (PEC)
Alert Response Address (ARA)
PMBus (with PEC)
Figure 9. Stop Bit within Address Byte when
Address Translation Byte Is 1
TRANSLATION BYTE
SDAOUT
SCLIN
SDAIN
N2 GATE N2 OFF N2 OFF
N2 ON
ADDRESS BIT
BECOMES
STOP BIT
STOP
BIT
START
BIT
1
4316 F09
N1 GATE N1 ON N1 ON
N1
OFF
START
BIT
STOP
BIT START
BIT
LTc4316
LTC4316
12
4316f
For more information www.linear.com/LTC4316
TYPICAL APPLICATIONS
Figure 10. Application with Option for Pass-Through Mode
4316 F10
SCLOUT
R1
2k
R2
2k
R3
2k
R4
2k
SDAOUT
ENABLE
SCLIN
SDAIN
READY
V
CC2
TO SLAVE #1
SCL
TO SLAVE #1
SDA
V
CC1
TO MASTER
SCL
TO MASTER
SDA
0V
PASS-THROUGH
ADDRESS
TRANSLATION
VCC2
VCC1 MUST BE HIGHER OR SAME TO VCC2
GND XORH
LTC4316
VCC
XORL
R5
2k
RLT
976k
RLB
182k
R4
10k
R7
10k
R6
10k
C1
0.01µF
3.3V
5V
SCLOUT
SDAOUT
XORH
READY
SCLIN
SDAIN CARD 1_SCL
CARD 1_SDA
ADDRESS TRANSLATION
BYTE 0x02
GND
LTC4316
VCC
ENABLE
READY
SCL
SDA
ENABLE1
XORL
RLT 1
976k
R1
10k
R2
10k
R3
10k
RLB1
102k
C3
0.01µF
4316 F11
R5
10k
R9
10k
R8
10k
C2
0.01µF
ENABLEN
SCLOUT
SDAOUT
XORH
READY
SCLIN
SDAIN CARD N_SCL
CARD N_SDA
ADDRESS TRANSLATION
BYTE 0x04
GND
LTC4316
VCC
ENABLE
XORL
RLT 2
976k
RLB2
182k
C4
0.01µF
Figure 11. LTC4316 in an I2C Hot Swap Application with a Staggered Connector
LTC43 1 6 DDPackage 4 I j#77717, i w l 4:1 $912+ 7 A \ UUW Ufi 777‘777 f 7 777L777 T \X \ + 1 E O \ mm m w: r T L7HEJWEGR 1 3
LTC4316
13
4316fa
For more information www.linear.com/LTC4316
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/ltc4316#packaging for the most recent package drawings.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55
±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTc4316 MS Packa‘Je manna; HUM 7:9
LTC4316
14
4316fa
For more information www.linear.com/LTC4316
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/ltc4316#packaging for the most recent package drawings.
MSOP (MS) 0213 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ±0.152
(.193 ±.006)
0.497 ±0.076
(.0196 ±.003)
REF
8910 76
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
0.1016 ±0.0508
(.004 ±.002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev F)
LTC43 1 6 L7HEJWEGR 1 5
LTC4316
15
4316fa
For more information www.linear.com/LTC4316
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/15 Minor edits. 4, 5
LTC4316 SWGLE YCDNNECTED DUAL DUAL
LTC4316
16
4316fa
For more information www.linear.com/LTC4316
LINEAR TECHNOLOGY CORPORATION 2015
LT 1015 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC4316
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot Swappable 2-Wire Bus Buffers LTC4300A-1: Bus Buffer with READY and ENABLE
LTC4300A-2: Dual Supply Buffer with ACC
LTC4300A-3: Dual Supply Buffer and ENABLE
LTC4302-1/
LTC4302-2
Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
LTC4303/
LTC4304
Hot Swappable 2-Wire Bus Buffer with Stuck
Bus Recovery
Provides Automatic Clocking to Free Stuck I2C Busses
LTC4305/
LTC4306
2- or 4-Channel, 2-Wire Bus Multiplexers
with Capacitance Buffering
Tw o or Four Software Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kV HBM ESD
LTC4307 Low Offset, Hot Swappable 2-Wire Bus
Buffer with Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators,
±5kV HBM ESD
LTC4307-1 High Definition Multimedia Interface (HDMI)
Level Shifting 2-Wire Bus Buffer
60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM ESD
LTC4308 Low Voltage, Level Shifting Hot Swappable
2-Wire Bus Buffer with Stuck Bus Recovery
Bus Buffer with 1V Precharge, ENABLE and READY, 0.9V to 5.5V Level Translation, 30ms
Stuck Bus Disconnect and Recovery, Output Side Rise Time Accelerators, ±6kV HBM ESD
LTC4309 Low Offset Hot Swappable 2-Wire Bus
Buffer with Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators,
±5kV HBM ESD, 1.8V to 5.5V Level T
ranslation
LTC4310-1/
LTC4310-2
Hot Swappable I2C Isolators Bidirectional I2C Communication Between Tw o Isolated Busses, LTC4310-1: 100kHz Bus,
LTC4310-2: 400kHz Bus
LTC4311 Hot Swappable I2C/SMBus Accelerator Rise Time Acceleration with ENABLE, ±8kV HBM ESD
LTC4312/
LTC4314
2- or 4-Channel, Hardware Selectable 2-Wire
Bus Multiplexers with Capacitance Buffering
Tw o or Four Pin Selectable Downstream Busses, VIL Up to 0.3V • VCC, Rise Time
Accelerators, 45ms Stuck Bus Disconnect and Recovery, ±4kV HBM ESD
LTC4313-1/
LTC4313-2/
LTC4313-3
High Noise Margin 2-Wire Bus Buffers VIL = 0.3V • VCC, Rise Time Accelerators, Stuck Bus Disconnect and Recovery, 1V
Precharge, ±4kV HBM ESD
Figure 12. Comparison Between LTC4316/LTC4317/LTC4318
SCLOUT
SDAOUT
READY
SCLOUT
SDAOUT
READY
VCC
SCLIN
SDAIN
XORH
XORL
ENABLE
GND
SCLIN
SDAIN
XORH
XORL
ENABLE
SINGLE
LTC4316
SCLOUT1
SDAOUT1
READY1
SCLOUT
SDAOUT
READY
VCC
SCLIN
SDAIN
XORH1
XORL1
ENABLE1
SCLIN
SDAIN
XORH
XORL
ENABLE
Y CONNECTED DUAL
LTC4317
SCLOUT2
SDAOUT2
READY2
SCLOUT
SDAOUT
READY
SCLIN
SDAIN
XORH
XORL
ENABLE
CHANNEL2
CHANNEL1
SCLOUT1
SDAOUT1
READY1
SCLOUT
SDAOUT
READY
VCC
SCLIN1
SDAIN1
XORH1
XORL1
ENABLE1
SCLIN
SDAIN
XORH
XORL
ENABLE
DUAL
LTC4318
SCLOUT2
SDAOUT2
READY2
SCLOUT
SDAOUT
READY
SCLIN2
SDAIN2
XORH2
XORL2
ENABLE2
GND
SCLIN
SDAIN
XORH
XORL
ENABLE
CHANNEL2
4316 F12
CHANNEL1
XORH2
XORL2
ENABLE2
GND

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