ADM1270 Datasheet by Analog Devices Inc.

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ANALOG DEVICES High Voltage Input Protection Device ADM1270
High Voltage Input Protection Device
Data Sheet
ADM1270
Rev. A Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©20142016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Controls supply voltages from 4 V to 60 V
Gate drive for low voltage drop reverse supply protection
Gate drive for P-channel FETs
Inrush current limiting control
Adjustable current limit
Foldback current limiting
Automatic retry or latch-off on current fault
Programmable current-limit timer for safe operating area (SOA)
Power-good and fault outputs
Analog undervoltage (UV) and overvoltage (OV) protection
16-lead, 3 mm × 3 mm LFCSP
16-lead QSOP
APPLICATIONS
Industrial modules
Battery-powered/portable instrumentation
GENERAL DESCRIPTION
The ADM1270 is a current-limiting controller that provides
inrush current limiting and overcurrent protection for modular
or battery-powered systems. When circuit boards are inserted
into a live backplane, discharged supply bypass capacitors draw
large transient currents from the backplane power bus as they
charge. These transient currents can cause permanent damage
to connector pins, as well as dips on the backplane supply that
can reset other boards in the system.
The ADM1270 is designed to control the inrush current, when
powering on the system, via an external P-channel field effect
transistor (FET).
To protect the system from a reverse polarity input supply, there
is a provision made to control an additional external P-channel
FET. This feature prevents reverse current flow in case of a reverse
polarity connection, which can damage the load or the ADM1270.
The ADM1270 is available in a 3 mm × 3 mm, 16-lead LFCSP and
a 16-lead QSOP.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
1V
1V GATE DRIVE/
LOGIC
V
CB
TIMER
ON
TIMEOUT
I
OUT
CURRENT
LIMIT
TIMER
VCC/SENSE+ SENSE–
GATE
TIMER
GND
UV
OV
RPFG
FLB
LDO
VCAP
REF
SELECT
ISET
FAULT
FB_PG
ENABLE
TIMER_OFF
PWRGD
+
+
+
+
CURRENT-
LIMIT
CONTROL
ADM1270
12259-001
Figure 1.
ADM1270 Data Sheet
Rev. A | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Simplified Functional Block Diagram ........................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 9
Typical Application Circuit ........................................................... 14
Theory of Operation ...................................................................... 15
Powering the ADM1270 ............................................................ 16
Current Sense Inputs ................................................................. 16
Current-Limit Reference ........................................................... 16
Setting the Current Limit (ISET) ............................................. 16
Foldback ...................................................................................... 17
TIMER ......................................................................................... 17
TIMER_OFF ............................................................................... 18
Hot Swap Retry Duty Cycle ...................................................... 18
Gate and RPFG Clamps ............................................................. 19
Fast Response to Severe Overcurrent ...................................... 19
Undervoltage and Overvoltage ................................................. 19
Enable Input ................................................................................ 19
Power Good ................................................................................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
4/16Rev. 0 to Rev. A
Change to Setting the Current Limit (ISET) Section ................. 17
12/14Revision 0: Initial Version
Data Sheet ADM1270
Rev. A | Page 3 of 21
SPECIFICATIONS
VCC/VSENSE+ = 4 V to 60 V, VSENSE = (VSENSE+ − VSENSE−) = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Operating Voltage Range VCC 4 60 V
Quiescent Current ICC 360 500 μA GATE on
UV PIN
Input Current IUV 0.005 0.2 μA UV ≤ 5.5 V, TA = −40°C to +85°C
0.005 1 μA UV ≤ 5.5 V, TA = −40°C to +125°C
UV Threshold UVTH 0.985 1.0 1.015 V UV falling
UV Threshold Hysteresis UVHYST 55 60 65 mV
UV Glitch Filter UVGF 4 7 μs 50 mV overdrive
UV Propagation Delay UVPD 6 8 μs UV low to GATE pull-down circuit active
OV PIN
Input Current IOV 0.005 0.2 μA OV ≤ 5.5 V, TA = −40°C to +85°C
0.005 1 μA OV ≤ 5.5 V, TA = −40°C to +125°C
OV Threshold OVTH 0.985 1.0 1.015 V OV rising
OV Threshold Hysteresis OVHYST 25 30 35 mV
OV Glitch Filter OVGF 0.5 2.0 μs 50 mV overdrive
OV Propagation Delay OVPD 1.5 2.5 μs OV high to GATE pull-up circuit active
SENSE−
Input Current ISENSE− 20 40 70 μA SENSE− = 60 V
VCAP PIN
Internally Regulated Voltage VVCAP 3.546 3.6 3.636 V 0 μA ≤ IVCAP ≤ 1 mA, CVCAP = 1 μF
Undervoltage Lockout UVLO
Rising UVLORISE 3.4 V VCC rising
Falling UVLOFALL 3.0 V VCC falling
Hysteresis UVLOHYST 230 mV
ISET PIN
Input Current IISET 0.005 0.2 μA VISET ≤ VVCAP, TA = −40°C to +85°C
0.005 1 μA VISET ≤ VVCAP, TA = −40°C to +125°C
Reference Select Threshold VISETRSTH 2.55 2.6 2.65 V If VISET > VISETRSTH, an internal reference (VCLREF) is used
Internal Reference VCLREF 2 V
Accuracies included in total sense voltage
accuracies
Gain of Current Sense Amplifier AVCSAMP 40 V/V
Accuracies included in total sense voltage
accuracies
RPFG PIN
Reverse Protection FET Gate Drive
Voltage
VRPFG 0 V VCC ≤ 10 V
Reverse Protection FET Gate Drive
Voltage Offset
ΔVRPFG 10 12 14 V ΔVRPFG = VCCVRPFG, 60 V ≥ VCC ≥ 14 V, IRPFG ≤ 5 μA
RPFG Pull-Down (On) Current IRPFGND 7 9 12 μA VRPFG = VCC
GATE PIN
GATE Drive Voltage ΔVGATE 10 12 14 V ΔVGATE = VCCVGATE, 60 V ≥ VCC ≥ 14 V, IGATE ≤ 5 μA
GATE Pull-Down (On) Current IGATEDN 20 25 30 μA VGATE = VCC
GATE Pull-Up (Off ) Current IGATEUP
Regulation IGATEUP_REG −50 −65 −80 μA ΔVGATE ≥ 2 V, (VSENSE+VSENSE−) = 70 mV
Fault IGATEUP_FLT −7 −13 −20 mA ΔVGATE = 2 V
FAU LT FAU LT
ADM1270 Data Sheet
Rev. A | Page 4 of 21
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CURRENT SENSE VOLTAGE
Sense Voltage Current Limit
(VSENSE+ − VSENSE−)
VSENSECL 47 50 53 mV VISET > 2.65 V, VFLB > 1.1 V, ΔVGATE = 3 V, IGATE = 0 µA
Foldback Inactive 62.5 mV VISET = 2.5 V, VFLB > 1.35 V, ΔVGATE = 3 V, IGATE = 0 µA
47 50 53 mV VISET = 2 V, VFLB > 1.1 V, ΔVGAT E = 3 V, IGATE = 0 µA
22.5 25.0 27.5 mV VISET = 1 V, VFLB > 0.57 V, ΔVGATE = 3 V, IGATE = 0 µA
10.0 12.5 15.0 mV VISET = 0.5 V, VFLB > 0.3 V, ΔVGATE = 3 V, IGATE = 0 µA
Foldback Active 7 10 13 mV VFLB = 0 V, ΔVG AT E = 3 V, IGATE = 0 µA
22 25 28 mV VISET > 2 V, VFLB = 0.5 V, ΔVGAT E = 3 V, IGATE = 0 µA
Circuit Breaker Offset VCBOS 0.5 1 1.5 mV Circuit breaker trip voltage, VCB = VSENSECL − VCBOS
SEVERE OVERCURRENT
Voltage Threshold VSENSEOC 90 100 110 mV VISET > 2.65 V
20 25 30 mV VISET = 0.5 V
Glitch Filter Duration 0.4 1.6 µs
Response Time 2.0 3.5 µs
TIMER PIN
TIMER Pull-Up Current ITIMERUP −18 20 −22 µA Overcurrent fault, 0.2 V ≤ VTIMER 2 V
TIMER High Threshold VTIMERH 1.96 2.0 2.04 V
TIMER Low Threshold VTIMERL 0.075 0.10 0.12 V
TIMER Pull-Down Current ITIMERPD 0.85 1.15 µA Timer pin voltage = 0.2 V
75 105 µA Timer pin voltage = 0.05 V
TIMER_OFF PIN
Power-On Reset Pull-Up Current IPOR 18 −20 −22 µA Initial power-on reset, VTIMER_OFF = 1 V
Retry Pull-Up Current ITMROFF −0.85 −1 −1.15 µA After fault when GATE is off, VTIMER_OFF = 1 V
TIMER_OFF High Threshold VTMROFFH 1.96 2.0 2.04 V
FOLDBACK (FLB PIN)
Input Current IFLB 0.005 0.2 µA VFLB 5.5 V, TA = −40°C to +85°C
0.005 1 µA VFLB 5.5 V, TA = −40°C to +125°C
PWRGD FEEDBACK INPUT (FB_PG PIN)
Input Current IFBPG 0.005 0.2 µA VFB_PG 5.5 V, TA = −40°C to +85°C
0.005 1 µA VFB_PG 5.5 V, TA = −40°C to +125°C
PWRGD Rising Threshold VPGTH 0.985 1.0 1.015 V FB_PG rising
PWRGD Threshold Hysteresis PGHYST 25 30 35 mV
Power-Good Glitch Filter PGGF 0.5 1.5 µs 50 mV overdrive
FAULT PIN
Output Low Voltage VOL_FAULT 0.1 V IFAULT = 100 µA
0.4 V IFAU LT = 1 mA
Leakage Current IFAULT 0.005 1 µA VFAULT = 5.5 V, FAULT output high-Z
ENABLE PIN
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.4 V
Leakage Current IEN 0.005 1 µA VEN = 5.5 V
PWRGD PIN
Output Low Voltage VOL_PWRGD 0.1 V IPWRGD = 100 µA
0.4 V IPWRGD = 1 mA
Output Low Voltage VOL_PWRGD 0.4 V VCC = 1.7 V, ISINK = 100 µA,
Leakage Current IPWRGD 0.005 1 µA VPWRGD = 60 V, PWRGD output high-Z
Table 2‘ FAU LT ESD CAUTION A M ESD (elenvostalic discharge) sensitive devi(e, Chavged dame; and awn boavd: can dlschavge wlmaui daemon Alxhough ms pmducl feaiuves paiemed 0! pm envy pmxemon mvcumy, damage may am" on devlces subjected m hlgh enevgy ESD Theveme, pvapev ESD piezaunom should be Kaken m avoid pevvmmance degvadauon m ‘05: av funcuonamy
Data Sheet ADM1270
Rev. A | Page 5 of 21
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC/SENSE+ −0.3 V to +66 V
VCAP
−0.3 V to +6 V
UV −0.3 V to +6 V
OV −0.3 V to +6 V
ISET −0.3 V to VCAP + 0.3 V
FLB 0.3 V to +6 V
FB_PG −0.3 V to +6 V
TIMER_OFF −0.3 V to VCAP + 0.3 V
TIMER 0.3 V to VCAP + 0.3 V
FAULT 0.3 V to +6 V
ENABLE −0.3 V to +6 V
PWRGD −0.3 V to +66 V
GATE
−0.3 V to V
CC
+ 0.3 V
GATE to VCC/SENSE+ −22 V to +0.3 V
SENSE− −0.3 V to VCC + 0.3 V
RPFG 0.3 V to VCC + 0.3 V
RPFG to VCC/SENSE+ −22 V to +0.3 V
VSENSE (VSENSE+ − VSENSE−) ±0.3 V
Continuous Current into Any Pin ±10 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Lead Temperature, Soldering (10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θJC ΨJB Unit
16-Lead, 3 mm × 3 mm LFCSP 49.5 35.2 29.6 °C/W
16-Lead QSOP 106.03 28.31 43.22 °C/W
ESD CAUTION
iADmna ; turvlzw ‘ Table 4‘ 167Lead LFCSP Pin Function Descriptions FAU LT
ADM1270 Data Sheet
Rev. A | Page 6 of 21
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. 16-Lead LFCSP Pin Configuration
Table 4. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 VCAP Internal Regulated Supply. Place a capacitor with a 1 µF or greater value on this pin to maintain good accuracy.
This pin can be used as a reference to program the ISET pin voltage.
2 ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.
3 UV Undervoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is under the UV limit.
4 OV Overvoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is above the OV limit.
5 ENABLE Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1270 controller to begin a
power-up sequence. If this pin is held low, the ADM1270 is prevented from powering up. There is no internal pull-
up on this pin.
6 FAU LT Fault Output. This pin indicates that the device has shut down due to an overcurrent fault condition. The device
can be configured for automatic retry after shutdown by connecting this pin directly to the ENABLE pin.
7 GND Ground Pin.
8 TIMER Timer Pin. An external capacitor, CTIMER, sets an SOA overcurrent fault delay. The GATE pin is pulled off when the
voltage on the TIMER pin exceeds the upper threshold.
9 TIMER_OFF Timer Off Pin. An external capacitor, CTIMER_OFF, sets an initial timing cycle delay and the SOA off time delay. After an
S
OA overcurrent fault has occurred, the GATE pin is pulled off until the voltage on the TIMER_OFF pin exceeds the
threshold.
10 FB_PG PWRGD Feedback Input Pin. An external resistor divider is connected from the output voltage to this pin to allow
an internal comparator to detect when the output voltage is above the PWRGD threshold.
11 FLB Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback reduces the
current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not
increased beyond the SOA limits.
12
PWRGD
Power-Good Signal. This signal indicates that the supply is within tolerance. This signal is based on the voltage
present on the FB_PG pin.
13 GATE Gate Output Pin. This pin is the gate drive of an external P-channel FET. This pin is driven by the FET drive
controller, which provides a pull-down current to charge the FET gate pin. The FET drive controller regulates to a
maximum load current by regulating the GATE pin. GATE is held off when the supply is below the undervoltage
lockout (UVLO).
14 SENSE− Negative Current Sense Input Pin. A sense resistor between the VCC/SENSE+ pin and the SENSE− pin sets the
analog current limit. The hot swap operation of the ADM1270 controls the external FET gate to maintain the sense
voltage (VSENSE+ − VSENSE). This pin also connects to the FET drain pin.
Data Sheet ADM1270
Rev. A | Page 7 of 21
Pin No. Mnemonic Description
15 VCC/SENSE+ Positive Supply Input Pin (VCC). A UVLO circuit resets the device when a low supply voltage is detected. GATE is
held off when the supply is below UVLO. No sequencing is required.
Positive Current Sense Input Pin (SENSE+). This pin connects to the main supply input. A sense resistor between
the VCC/SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1270
controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−).
16 RPFG Reverse Protection FET G
ate Driver Output. Connect this pin to the gate of the external reverse polarity protection
P-channel FET for low voltage drop operation.
N/A1 EP Exposed Pad. The exposed pad is located on the underside of the LFCSP package. Solder the exposed pad to the
printed circuit board (PCB) to improve thermal dissipation. The exposed pad can be connected to ground.
1 N/A = not applicable.
ADM1270 Data Sheet
Rev. A | Page 8 of 21
ISET
VCAP
UV
V
CC/SENSE+
RPFG
ENABLE
OV
FAULT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADM1270
(Not to Scale)
TOP VIEW FB_PG
GATE
SENSE–
PWRGD
FLB
GND
TIMER_OFF
TIMER
12259-003
Figure 3. 16-Lead QSOP Pin Configuration
Table 5. 16-Lead QSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC/SENSE+
Positive Supply Input Pin (VCC). A UVLO circuit resets the device when a low supply voltage is detected. GATE is
held off when the supply is below UVLO. No sequencing is required.
Positive Current Sense Input Pin (SENSE+). This pin connects to the main supply input. A sense resistor between
the VCC/SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1270
controls the external FET gate to maintain the sense voltage (VSENSE+VSENSE−).
2 RPFG Reverse Protection FET Gate Driver Output. Connect this pin to the gate of the external reverse polarity protection
P-channel FET for low voltage drop operation.
3 VCAP Internal Regulated Supply. Place a capacitor with a 1 μF or greater value on this pin to maintain good accuracy.
This pin can be used as a reference to program the ISET pin voltage.
4 ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.
5 UV Undervoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is under the UV limit.
6 OV Overvoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is above the OV limit.
7 ENABLE
Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1270 controller to begin a
power-up sequence. If this pin is held low, the ADM1270 is prevented from powering up. There is no internal pull-
up on this pin.
8 FAULT Fault Output. This pin indicates that the device has shut down due to an overcurrent fault condition. The device
can be configured for automatic retry after shutdown by connecting this pin directly to the ENABLE pin.
9 GND Ground Pin.
10 TIMER Timer Pin. An external capacitor, CTIMER, sets an SOA overcurrent fault delay. The GATE pin is pulled off when the
voltage on the TIMER pin exceeds the upper threshold.
11 TIMER_OFF
Timer Off Pin. An external capacitor, CTIMER_OFF, sets an initial timing cycle delay and the SOA off time delay. After an
SOA overcurrent fault has occurred, the GATE pin is pulled off until the voltage on the TIMER_OFF pin exceeds the
threshold.
12 FB_PG PWRGD Feedback Input Pin. An external resistor divider is connected from the output voltage to this pin to allow
an internal comparator to detect when the output voltage is above the PWRGD threshold.
13 FLB Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback reduces the
current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not
increased beyond the SOA limits.
14 PWRGD Power-Good Signal. This signal indicates that the supply is within tolerance. This signal is based on the voltage
present on the FB_PG pin.
15 GATE Gate Output Pin. This pin is the gate drive of an external P-channel FET. This pin is driven by the FET drive
controller, which provides a pull-down current to charge the FET gate pin. The FET drive controller regulates to a
maximum load current by regulating the GATE pin. GATE is held off when the supply is below UVLO.
16 SENSE− Negative Current Sense Input Pin. A sense resistor between the VCC/SENSE+ pin and the SENSE− pin sets the
analog current limit. The hot swap operation of the ADM1270 controls the external FET gate to maintain the sense
voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin.
3.55 3.5m
Data Sheet ADM1270
Rev. A | Page 9 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
3.55
3.57
3.59
3.61
3.63
3.65
–40°C –5°C 25°C 85°C 125°C
T
J
C)
V
VCAP
(V)
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
12259-004
Figure 4. VVCAP vs. Junction Temperature (TJ), Different Loads
3.590
3.595
3.600
3.605
3.610
00.2 0.4 0.6 0.8 1.0
I
LOAD
(mA)
V
VCAP
(V)
12259-005
Figure 5. VVCAP vs. Load Current (ILOAD)
3.590
3.595
3.600
3.605
3.610
V
IN
(V)
V
VCAP
(V)
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
50010 20 30 40
12259-006
Figure 6. VVCAP vs. Input Voltage (VIN), Different Loads
–40°C –5°C 25°C 85°C 125°C
T
J
C)
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
0
50
100
150
200
250
300
350
400
450
500
I
CC
(µA)
12259-007
Figure 7. Supply Current (ICC) vs. Junction Temperature (TJ), Different Loads
380
382
384
386
388
390
392
394
396
398
400
00.2 0.4 0.6 0.8 1.0
I
LOAD
(mA)
I
CC
(µA)
12259-008
Figure 8. Supply Current (ICC) vs. Load Current (ILOAD)
300
320
340
360
380
400
420
010 20 30 40 50
V
CC
(V)
I
CC
(µA)
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
12259-009
Figure 9. Supply Current (ICC) vs. Supply Voltage (VCC), Different Loads
mu mum 1 :.n
ADM1270 Data Sheet
Rev. A | Page 10 of 21
0
2
4
6
8
10
12
14
16
18
20
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
V
VCAP
OC THRESHOLD (mA)
V
IN
= 4.5V
V
IN
= 6V
V
IN
= 10V
12259-010
Figure 10. VVCAP Overcurrent (OC) Threshold vs. Temperature,
Different Input Voltages
11.0
11.2
11.4
11.6
11.8
12.0
12.2
12.4
12.6
12.8
13.0
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
V
GATE
(V)
V
IN
= 14V
V
IN
= 25V
V
IN
= 50V
12259-011
Figure 11. GATE Voltage (VGATE) vs. Temperature, Different Input Voltages
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
11.0
11.2
11.4
11.6
11.8
12.0
12.2
12.4
12.6
12.8
13.0
RPFG VOLTAGE (V)
V
IN
= 14V
V
IN
= 25V
V
IN
= 50V
12259-012
Figure 12. RPFG Voltage (VRPFG) vs. Temperature, Different Input Voltages
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
RPFG PULL-DOWN CURRENTA)
V
IN
= 14V
V
IN
= 25V
V
IN
= 50V
12259-013
Figure 13. RPFG Pull-Down Current (IRPFGND) vs. Temperature,
Different Input Voltages
0.045
0.050
0.055
0.060
0.065
0.070
2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70
V
ISET
(V)
CURRENT SENSE VOLTAGE (V)
4V
25V
50V
12259-014
Figure 14. Current Sense Voltage vs. ISET Voltage (VISET),
Different Input Voltages
2.50
2.55
2.60
2.65
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
REFERENCE SELECT THRESHOLD VOLTAGE (V)
12259-015
Figure 15. Reference Select Threshold Voltage (VISETRSTH) vs. Temperature,
VIN = 4 V
.mn .1a.n
Data Sheet ADM1270
Rev. A | Page 11 of 21
0.045
0.050
0.055
0.060
0.065
0.070
2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70
V
ISET
(V)
REFERENCE SELECT THRESHOLD VOLTAGE (V)
–40°C
–5°C
+25°C
+85°C
+125°C
12259-016
Figure 16. Reference Select Threshold Voltage (VISETRSTH) vs. ISET Voltage (VISET),
Different Temperatures
–22.0
–21.5
–21.0
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
–45 –25 –5 15 35 55 75 95 115 135
TEMPERATURE (°C)
TIMER CURRENT (µA)
4V
6V
10V
20V
50V
12259-017
Figure 17. Timer Current vs. Temperature, Different Input Voltages
–1.5
–1.4
–1.3
–1.2
–1.1
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–45 –25 –5
15 35 55 75 95 115 135
TEMPERATURE (°C)
TIMER OFF CURRENTA)
4V
6V
10V
20V
50V
12259-018
Figure 18. Timer Off Current (ITMROFF) vs. Temperature,
Different Input Voltages
–22.0
–21.5
–21.0
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
0510 15 20 25 30 35 40 45 50 55
INPUT VOLTAGE (V)
POR TIMER OFF CURRENT (µA)
–40°C
–5°C
+25°C
+85°C
+125°C
12259-019
Figure 19. POR Timer Off Current (IPOR) vs. Input Voltage (VIN),
Different Temperatures
–22.0
–21.5
–21.0
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
–45 –25 –5
15 35 55 75 95 115 135
TEMPERATURE (°C)
POR TIMER OFF CURRENT (µA)
4V
6V
10V
20V
50V
12259-020
Figure 20. POR Timer Off Current (IPOR) vs. Temperature,
Different Input Voltages
0
1
2
3
4
5
6
7
0.90 0.95 1.00 1.05 1.10
V
GATE
(V)
OV INPUT VOLTAGE (V)
OV INPUT RISE
OV INPUT FALL
12259-021
Figure 21. VGATE vs. OV Input Voltage
nmn m7 \
ADM1270 Data Sheet
Rev. A | Page 12 of 21
0.95
1.00
1.05
1.10
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
UV THRESHOLD VOLTAGE (V)
HYSTERESIS (V)
0
0.01
0.02
0.03
0.04
0.05
0.06
UV RISE
UV FALL
HYSTERESIS
12259-022
Figure 22. UV Threshold Voltage vs. Temperature
0.90
0.95
1.00
1.05
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
OV THRESHOLD VOLTAGE (V)
HYSTERESIS (V)
0
0.01
0.02
0.03
OV RISE
OV FALL
HYSTERESIS
12259-023
Figure 23. OV Threshold vs. Temperature
0.980
0.985
0.990
0.995
1.000
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
4V POWER-GOOD RISE
25V POWER-GOOD RISE
50V POWER-GOOD RISE
POWER-GOOD RISING THRESHOLD (V)
12259-024
Figure 24. Power-Good Rising Threshold vs. Temperature,
Different Input Voltages
0.950
0.955
0.960
0.965
0.970
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
POWER-GOOD FALLING THRESHOLD (V)
4V POWER-GOOD FALL
25V POWER-GOOD FALL
50V POWER-GOOD FALL
12259-025
Figure 25. Power-Good Falling Threshold vs. Temperature,
Different Input Voltages
0.100
0.102
0.104
0.106
0.108
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
SEVERE OC THRESHOLD (V)
4V OV
25V OC
50V OC
12259-026
Figure 26. Severe Overcurrent (OC) Threshold vs. Temperature,
Different Input Voltages
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
FLB (V)
V
SENSE
(V)
–40°C
–5°C
–25°C
–85°C
–125°C
12259-027
Figure 27. Sense Voltage (VSENSE ) vs. FLB, Different Temperatures
|||| \
Data Sheet ADM1270
Rev. A | Page 13 of 21
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
00.5 1.0 1.5 2.0 2.5 3.0 3.5
V
ISET
(V)
V
SENSE
(V)
–40°C
–5°C
+25°C
+85°C
+125°C
12259-028
Figure 28. Sense Voltage (VSENSE) vs. ISET Voltage (VISET),
Different Temperatures
0
5
10
15
20
25
30
35
40
45
50
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
OC INPUT CURRENT (µA)
10mV
20mV
30mV
40mV
50mV
60mV
12259-029
Figure 29. OC Input Current vs. Temperature, Different Sense Voltages (VSENSE)
0
5
10
15
20
25
30
35
40
45
50
00.5 1.0 1.5 2.0 2.5 3.0 3.5
OC INPUT CURRENT (µA)
–40°C
–5°C
+25°C
+85°C
+125°C
VSENSE (V)
12259-030
Figure 30. OC Input Current vs. Sense Voltage (VSENSE), Different Temperatures
1.98
2.00
1.99
2.01
2.02
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
OC TIMER THRESHOLD (V)
4V
50V
12259-031
Figure 31. OC TIMER Threshold vs. Temperature, Different Input Voltages
1.97
1.99
2.01
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
OC TIMER_OFF THRESHOLD (V)
4V
50V
12259-032
1.98
2.00
Figure 32. OC TIMER_OFF Threshold vs. Temperature,
Different Input Voltages
ADM1270 Data Sheet
Rev. A | Page 14 of 21
TYPICAL APPLICATION CIRCUIT
GND
R3 R5
1V
1V GATE DRIVE/
LOGIC
V
CB
TIMER
ON
TIMEOUT
I
OUT
CURRENT
LIMIT
TIMER
VCC/SENSE+ SENSE–
R
SENSE
GATE
TIMER
UV
OV
RPFG
FLB
R8
R7
R9
LDO
VCAP
REF
SELECT
ISET
FAULT
FB_PG
ENABLE
TIMER_OFF
PWRGD
+
+
+
+
CURRENT-
LIMIT
CONTROL
VOUT
LOAD
VIN
Q2
R1
R2
Q1
R4
C
TIMER
C
TIMER_OFF
12259-033
Figure 33. Typical Application Circuit
Data Sheet ADM1270
Rev. A | Page 15 of 21
THEORY OF OPERATION
When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. These transient currents
can cause permanent damage to connector pins, as well as voltage
dips on the backplane supply that can reset other boards in the
system.
The ADM1270 is designed to control the inrush current when
powering on the system, allowing a board to be inserted safely
into a live backplane by protecting it from excess currents.
The ADM1270 is a current-limiting controller that provides
inrush current limiting and overcurrent protection for modular
or battery-powered systems. The voltage developed across a
sense resistor in the power path is measured with a current
sense amplifier via the VCC/SENSE+ and SENSEpins. A
default limit of 50 mV is set, but this limit can be adjusted, if
required, using a resistor divider network from the VCAP pin
to the ISET pin.
The ADM1270 limits the current through the sense resistor by
controlling the gate voltage of an external P-channel FET in the
power path, via the GATE pin. The sense voltage and, therefore,
the load current is maintained below the preset maximum. The
ADM1270 protects the external FET by limiting the time that
the FET remains on while the current is at its maximum value.
This current-limit time is set by the choice of capacitors
connected to the TIMER pin and the TIMER_OFF pin. This
current-limit time helps to maintain the FET in its SOA.
In addition to the timer function, there is a foldback pin (FLB)
that is used to provide additional FET protection. The current
limit is linearly reduced by the voltage on the FLB pin, so that
for large drain to source voltage (VDS) voltage drops, the actual
current limit used by the device is lower, again helping to ensure
the FET is kept within its SOA.
A minimum voltage clamp ensures that even if the FLB voltage
is 0 V, the current is never reduced to zero, which otherwise
prevents the device from powering up.
The ADM1270 features OV and UV protection, programmed
using external resistor dividers on the UV and OV pins.
A PWRGD signal can be used to indicate when the output
supply is greater than a voltage programmed using an external
resistor divider on the FB_PG pin.
To protect the system from a reverse polarity input supply, there
is a provision made to control an additional external P-channel
FET with the RPFG pin. This feature allows for a low on-resistance,
low voltage drop FET to be used in place of a diode to perform
the same function, thus saving power losses and improving overall
efficiency. The reverse voltage protection FET prevents negative
input voltages that can damage the load or the ADM1270.
1V
1V GATE DRIVE/
LOGIC
V
CB
TIMER
ON
TIMEOUT
I
OUT
CURRENT
LIMIT
TIMER
VCC/SENSE+ SENSE–
GATE
TIMER
GND
UV
OV
RPFG
FLB
LDO
VCAP
REF
SELECT
ISET
FAULT
FB_PG
ENABLE
TIMER_OFF
PWRGD
+
+
+
+
CURRENT-
LIMIT
CONTROL
ADM1270
12259-034
Figure 34. Simplified Functional Block Diagram
ADM1270 Data Sheet
Rev. A | Page 16 of 21
POWERING THE ADM1270
A supply voltage from 4 V to 60 V is required to power the
ADM1270 via the VCC/SENSE+ pin. The VCC/SENSE+ pin
provides the majority of the bias current for the device; the
remainder of the current needed to control the gate drive and to
best regulate the gate to source voltage (VGS) is supplied by the
SENSE− pin.
CURRENT SENSE INPUTS
The load current is monitored by measuring the voltage drop
across an external current sense resistor, RSENSE (see Figure 35).
An internal current sense amplifier provides a gain of 40 to the
voltage drop detected across RSENSE. The result is compared to an
internal reference and is used by the hot swap control logic to
detect an overcurrent condition.
40×
+
CURRENT
LIMIT
VCC/SENSE+ SENSE–
GATE
GND
LDO
VCAP
REFERENCE
R
SENSE
Q1
4V TO 60V
+
12259-035
Figure 35. Hot Swap Current Sense Amplifier
CURRENT-LIMIT REFERENCE
The current-limit reference voltage determines the load current
at which the ADM1270 limits the current during an overcurrent
event. This reference voltage is compared to the amplified current
sense voltage to determine when the current-limit threshold is
reached.
An internal current-limit reference selector block continuously
compares the ISET and FLB voltages to determine which
voltage is the lowest at any given time; the lowest voltage is used
as the current-limit reference. This behavior ensures that the
programmed current limit, ISET, is used in normal operation,
and that the foldback feature reduces the current limit when
required during startup and/or fault conditions.
40×
+ –
CURRENT
LIMIT
VCC/SENSE+ SENSE–
GATE
GND
LDO
VCAP
R
SENSE
Q1
4V TO 60V
+
CURRENT-
LIMIT
CONTROL
REF
SELECT
ISET
FLB
2V
12259-036
Figure 36. Current-Limit Reference Selection
The FLB voltage varies during different modes of operation
and, therefore, is clamped to a minimum level of 200 mV. This
behavior prevents zero current flow due to the current limit
being set too low. Figure 37 provides an example of how the
FLB and ISET voltages interact during startup as the ADM1270
turns on the FET and charges the load capacitance. Depending
on how the foldback feature is configured, the transition point
varies to ensure that the FET operates within the correct limits.
2V
0.2V
I
SET
V
ISET
FLB
TIME
CURRENT-LIMIT
REFERENCE
12259-037
Figure 37. Interaction of Foldback (FLB) and ISET Current Limits
SETTING THE CURRENT LIMIT (ISET)
The maximum current limit is partially determined by selecting
a sense resistor to match the current sense voltage limit on the
controller for the desired load current. However, as currents
become larger, the sense resistor value decreases for a given
current sense voltage. Choosing an appropriate current sense
resistor can be difficult due to the limited selection of low value
resistors. The ADM1270 provides an adjustable current sense
voltage limit to handle this issue. The device allows the user to
program the required current sense voltage limit from 12.5 mV
to 62.5 mV.
Data Sheet ADM1270
Rev. A | Page 17 of 21
The default value is 50 mV and is achieved by connecting the
ISET pin directly to the VCAP pin. This circuit configuration
configures the device to use an internal 2 V reference, which
results in 50 mV at the sense inputs (see Figure 38).
40×
+
CURRENT
LIMIT
VCC/SENSE+ SENSE–
GATE
GND
LDO
VCAP
R
SENSE
Q1
4V TO 60V
+
REF
SELECT
ISET
FLB
2V
12259-038
CURRENT-
LIMIT
CONTROL
Figure 38. Fixed 50 mV Current Sense Limit
To program the sense voltage from 12.5 mV to 62.5 mV, an
external resistor divider sets the reference voltage on the ISET
pin (see Figure 39).
40×
+
CURRENT
LIMIT
VCC/SENSE+ SENSE–
GATE
GND
LDO
VCAP
RSENSE
Q1
4V TO 60V
+
REF
SELECT
ISET
FLB
2V
12259-039
CURRENT-
LIMIT
CONTROL
Figure 39. Adjustable 12.5 mV to 62.5 mV Current Sense Limit
The VCAP pin has a 3.6 V internally generated voltage that can
set a voltage at the ISET pin. Assuming that VISET equals the
voltage on the ISET pin, select the resistor divider values to set
the ISET voltage as follows:
VISET = VSENSE × 40
where VSENSE is the current sense voltage limit.
The VCAP rail also can be used as the pull-up supply for setting
other pins. To guarantee that VCAP meets its accuracy
specifications, do not apply a load to the VCAP pin greater
than 100 µA.
FOLDBACK
Foldback is a method to actively reduce the current limit as the
voltage drop across the FET increases. This technique keeps the
power dissipation in the FET at a minimum during power-up,
overcurrent, or short-circuit events. It also reduces the need to
oversize the FET to accommodate worst-case conditions,
resulting in board size and cost savings.
Assuming that the supply voltage remains constant and within
tolerance, the ADM1270 detects the voltage drop across the FET
by sensing output voltage through a resistor divider. The device,
therefore, relies on the principle that the drain of the FET is at
the maximum expected supply voltage, and that the magnitude
of the output voltage is relative to that of the VDS of the FET.
Using a resistor divider from the output voltage to the FLB pin,
the relationship from VOUT, and thus VDS, to VFLB can be derived.
Design the resistor divider to result in a voltage equal to VISET/2
when VOUT falls below the desired level. This voltage must be
well below the working tolerance of the supply rail. As VOUT
continues to drop, the current-limit reference follows VFLB
because it is now the lowest voltage input to the current-limit
reference selector block, resulting in a reduction of the current
limit and, therefore, the regulated load current. To prevent the
current from decreasing to zero, a clamp activates when VFLB
reaches 200 mV. The current limit cannot drop below this level.
To ensure that the SOA characteristics of a particular FET are
not violated, the minimum current for this clamp varies from
design to design. However, the current-limit reference fixes this
clamp at 200 mV, which equals 10 mV across the sense resistor.
Therefore, the main ISET voltage can be adjusted to adjust the
clamp to the required percentage current reduction. For example,
if VISET equals 1.6 V, set the clamp at 25% of the maximum current.
TIMER
The TIMER pin handles the timing function with an external
capacitor, CTIMER. The two TIMER pin comparator thresholds
are VTIMERL (0.1 V) and VTIMERH (2.0 V). There are two timing
current sources as well: a 20 µA pull-up current and a 1 µA
pull-down current.
These current and voltage levels, in combination with the user
chosen value of CTIMER, determine the fault current-limit time
and the on-time of the hot swap retry duty cycle. The TIMER
pin capacitor value is determined using the following equation:
CTIMER = (tON × 20 µA)/VTIMERH
where:
tON is the time that the FET is allowed to spend in regulation at
the current limit.
VTIMERH is the TIMER high threshold.
The choice of FET is based on matching this time with the SOA
characteristics of the FET. Foldback can also be used to simplify
the selection.
cundmun allow: The TIMER pin to r FAULT cummll EAUL’l‘ FAULT BLE pm. FAULT ), ms GA FAU LT anllally by
ADM1270 Data Sheet
Rev. A | Page 18 of 21
When the voltage across the sense resistor reaches the circuit
breaker trip voltage, VCB, the 20 µA TIMER pull-up current is
activated. The ADM1270 begins to regulate the load current at
the current limit, initiating a rising voltage ramp on the TIMER
pin. If the sense voltage falls below this circuit breaker trip voltage
before the TIMER pin reaches VTIMERH, the 20 µA pull-up current is
disabled, and the 1 µA pull-down current is enabled. If the voltage
on the TIMER pin falls below VTIMERL, the TIMER pin is
discharged to GND using a strong pull-down current on the
TIMER pin.
However, if the overcurrent condition is continuous and the sense
voltage remains above the circuit breaker trip voltage, the 20 µA
pull-up current remains active, and the FET remains in
regulation. This condition allows the TIMER pin to reach VTIMERH
and to initiate the GATE shutdown, and the FAULT pin is pulled
low immediately.
The circuit breaker trip voltage is not the same as the hot swap
sense voltage current limit. There is a small circuit breaker offset,
VCBOS, which causes the timer to start shortly before the current
reaches the defined current limit.
In latch-off mode, the TIMER pin is discharged to GND when
it reaches the VTIMERH threshold. The TIMER_OFF pin begins to
charge up. While the TIMER_OFF pin is ramping up, the hot swap
controller remains off and cannot be turned back on, and the
FAULT pin remains low. When the voltage on the TIMER_OFF
pin rises above the VTMROFFH threshold, the hot swap controller
can be reenabled by toggling the ENABLE pin from high to low
and then high again.
TIMER_OFF
The TIMER_OFF pin handles two timing functions with an
external capacitor, CTIMER_OFF. There is one TIMER_OFF pin
comparator threshold at VTMROFFH (2.0 V). There are two timing
current sources, a 20 µA pull-up current and a 1 µA pull-up
current.
These current and voltage levels, in combination with the user
chosen value of CTIMER_OFF, determine the initial power-on reset
time and also set the fault current-limit off time.
When VCC is connected to the input supply, the internal supply
(VCAP) of the ADM1270 must charge up. VCAP starts up and
settles in a very short time. When the UVLO threshold voltage is
exceeded at VCAP, the device emerges from reset. During this first
brief reset period, the GATE and TIMER pins are both held low.
The ADM1270 then proceeds through an initial timing cycle.
The TIMER_OFF pin is pulled high with 20 µA. When the
TIMER_OFF pin reaches the VTMROFFH threshold (2.0 V), the
initial timing cycle is complete. This initial power-on reset
duration is determined by the following equation:
tINITIAL = VTMROFFH × (CTIMER_OFF/20 µA)
For example, a 100 nF capacitor results in a delay of approximately
10 ms. If the UV and OV inputs indicate that VCC is within the
defined window of operation when the initial timing cycle
terminates, the device is ready to start a hot swap operation.
At the completion of this initial power-on reset cycle, the
TIMER_OFF pin is ready to perform a second function. When
the voltage at the TIMER pin exceeds the fault current-limit
time threshold voltage of VTIMERH (2.0 V), the 1 µA pull-up
current is activated on TIMER_OFF, and CTIMER_OFF begins to
charge initiating a voltage ramp on the TIMER_OFF pin. When
the TIMER_OFF pin reaches VTMROFFH, the TIMER_OFF fault
current-limit off time is complete.
This fault current-limit off time is determined by the following
equation:
tTIMER_OFF = VTMROFFH × (CTIMER_OFF/1 µA)
For example, a 100 nF capacitor results in an off time of
approximately 200 ms from the time that TIMER exceeds
VTIMERH to the time that TIMER_OFF reaches VTMROFFH.
HOT SWAP RETRY DUTY CYCLE
The ADM1270 turns off the FET after an overcurrent fault and
then uses the capacitor on the TIMER_OFF pin to generate a
delay before automatically retrying the hot swap operation. To
configure the ADM1270 for automatic retry mode, tie the FAULT
pin to the ENABLE pin. Note that a pull-up resistor to VCAP is
required on the FAULT pin.
When an overcurrent fault occurs, the capacitor on the TIMER
pin charges with a 20 µA pull-up current. When the TIMER pin
reaches VTIMERH (2.0 V), the GATE pin is pulled high, turning
off the FET. When the FAULT pin is tied to the ENABLE pin
for automatic retry mode, the TIMER_OFF pin begins to
charge with a 1 µA current source. When the TIMER_OFF pin
reaches VTMROFFH (2.0 V), the ADM1270 automatically restarts
the hot swap operation.
The automatic retry duty cycle is set by the ratio of 1 µA/20 µA
and the ratio of CTIMER/CTIMER_OFF. The retry duty cycle is set by
the following equation:
Duty_Cycle = (CTIMER × 1 µA)/(CTIMER_OFF × 20 µA)
The value of the CTIMER and CTIMER_OFF capacitors
determine the on and off time of this cycle, which are calculated
as follows:
tON = VTIMERH × (CTIMER/20 µA)
tOFF = VTMROFFH × (CTIMER_OFF/1 µA)
A 100 nF capacitor on the TIMER pin gives an on time of
10 ms. A 100 nF capacitor on the TIMER_OFF pin gives an off
time of 200 ms. The device retries continuously in this manner
and can be disabled manually by holding the ENABLE pin low,
or by disconnecting the FAULT pin. To prevent thermal stress
in the FET, a capacitor on the TIMER_OFF pin can be used to
extend the retry time to any desired level.
Data Sheet ADM1270
Rev. A | Page 19 of 21
GATE AND RPFG CLAMPS
The circuits driving the GATE and RPFG pins are clamped to less
than 14 V below the VCC/SENSE+ pin. These clamps ensure that
the maximum VGS rating of the external FETs is not exceeded.
The reverse protection FET gate pin (RPFG) drives the gate of
an external PMOSFET. This PMOSFET, Q2, provides reverse
polarity protection to the ADM1270 and the system being
powered. If the VCC and GND pins have been reverse
connected (that is, where power is actually applied to GND),
VCC is negative with respect to the system ground. In this
condition, Q2 prevents current from flowing in the reverse
direction because the gate of Q2 is held at GND, and Q2 is off.
VOUT is not pulled below GND, and the system is protected
against a reverse polarity connection.
In the typical case where power is applied to VCC, the gate is
still pulled down and allows the FET Q2 to turn on and conduct
current in the forward direction. Operating Q2 in this way
provides a low on-resistance, low voltage drop compared to a
diode for reverse polarity protection, giving the system higher
efficiency and more headroom for operation. Figure 33 shows
the connection of Q2 and RPFG for proper operation.
FAST RESPONSE TO SEVERE OVERCURRENT
The ADM1270 includes a separate, high bandwidth, current
sense amplifier to detect a severe overcurrent that is indicative of
a short circuit. The fast response time allows the ADM1270 to
handle events of this type that could otherwise cause catastrophic
damage if not detected and dealt with very quickly. The fast
response circuit ensures that the ADM1270 can detect an
overcurrent event of approximately 200% of the normal current
limit and control the current within approximately 2 µs.
UNDERVOLTAGE AND OVERVOLTAGE
The ADM1270 monitors the supply voltage for UV and OV
conditions. The UV and OV pins are connected to the inputs
of the voltage comparators and compared to an internal 1 V
voltage reference.
Figure 40 illustrates the voltage monitoring input connections.
An external resistor network divides the supply voltage for
monitoring. An undervoltage event is detected when the voltage
connected to the UV pin falls below 1 V, and the FET is turned
off using the 10 mA pull-up current. Similarly, when an overvoltage
event occurs and the voltage on the OV pin exceeds 1 V, the
FET is turned off using the 10 mA pull-up current.
40×
+ –
VCC/SENSE+ SENSE–
GATE
GND
LDO
GATE DRIVE/
LOGIC
VCAP
R
SENSE
Q1
4V TO 60V
+
+
UV
1V
1V
OV
12259-040
Figure 40. Undervoltage and Overvoltage Supply Monitoring
ENABLE INPUT
The ADM1270 provides a dedicated ENABLE digital input pin.
The ENABLE pin allows the ADM1270 to remain off by using a
hardware signal, even when the voltage on the UV pin is greater
than 1.0 V, and the voltage on the OV pin is less than 1.0 V.
Although the UV pin can be used to provide a digital enable
signal, using the ENABLE pin for this purpose keeps the ability
of the UV pin free to monitor undervoltage conditions.
In addition to the conditions for the UV and OV pins, the
ADM1270 ENABLE input pin must be high for the device to
begin a power-up sequence.
A similar function can be achieved using the UV pin directly.
Alternatively, if the UV divider function is still required, the
configuration shown in Figure 41 can be used.
D1
V
IN
SYSTEM CONTROL
ADM1270
EN UV
R1
R2
12259-041
Figure 41. Using the UV Pin as an Enable
Diode D1 prevents the external driver pull-up resistor from
affecting the UV threshold. Select Diode D1 using the following
criteria:
(VF × D1) + (VOL × EN) << 1.0 V (IF = VIN/R1)
Ensure that the EN sink current does not exceed the specified
VOL value. If the open-drain device has no pull-up, the diode is
not required.
ADM1270 Data Sheet
Rev. A | Page 20 of 21
POWER GOOD
The power-good (PWRGD) output can be used to indicate
whether the output voltage exceeds a user defined threshold
and can, therefore, be considered good. The PWRGD output
is set by a resistor divider connected to the FB_PG pin (see
Figure 42).
40×
+ –
VCC/SENSE+ SENSE–
GATE
GND
LDO
GATE DRIVE/
LOGIC
VCAP
R
SENSE
Q1
FB_PG
4V TO 60V
+
+
UV
1V
1V
OV
12259-042
Figure 42. Generation of PWRGD Signal
When the voltage at the FB_PG pin exceeds the 1 V threshold
(indicating that the output voltage has risen), the open-drain
pull-down current is disabled, allowing PWRGD to be pulled
high. The PWRGD pin is an open-drain output that pulls low
when the voltage at the FB_PG pin is lower than the 1 V
threshold minus the hysteresis (power bad). Hysteresis on the
FB_PG pin is fixed at 30 mV. PWRGD is guaranteed to be in a
valid state for VCC ≥ 1.7 V.
Calculate the power-good threshold using the following
equation:
VPWRGD = 1 V × (1 + RPG1/RPG2)
where:
RPG1 is the resistance from VOUT to FB_PG.
RPG2 is the resistance from FB_PG to GND.
ORDERING GUIDE mouilms Anilog Devkes, um. All .ing .mmd. Tvidtmavks and ANALOG DEVICES www.ana|ng.nnm
Data Sheet ADM1270
Rev. A | Page 21 of 21
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.65
1.50 SQ
1.45
1
0.50
BSC
BOT
TOM VIEW
TOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-26-2012-A
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very, Very Thin Quad
(CP-16-27)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
16 9
8
1
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0.64)
BSC
0.041 (1.04)
REF
0.010 (0.25)
0.006 (0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
COPLANARITY
0.004 (0.10)
0.065 (1.65)
0.049 (1.25)
0.069 (1.75)
0.053 (1.35)
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
09-12-2014-A
Figure 44. 16-Lead Body, Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches (and millimeters)
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Brand Code
ADM1270ACPZ-R2 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-27 LNQ
ADM1270ACPZ-R7 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-27 LNQ
ADM1270ARQZ 40°C to +125°C 16-Lead Body, Shrink Small Outline Package [QSOP] RQ-16
ADM1270ARQZ-R7 −40°C to +125°C 16-Lead Body, Shrink Small Outline Package [QSOP] RQ-16
ADM1270CP-EVALZ
Evaluation Board for 16-Lead LFCSP_WQ
ADM1270RQ-EVALZ Evaluation Board for 16-Lead QSOP
1 Z = RoHS Compliant Part.
©20142016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12259-0-4/16(A)

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