Hoja de datos de ADAU1701 de Analog Devices Inc.

ANALOG SP 28-l56-Bit Audio Processor DEVICES with Two A085 and Four DABs ADAUI'IOI
SigmaDSP 28-/56-Bit Audio Processor
with Two ADCs and Four DACs
Data Sheet
ADAU1701
Rev. C Document Feedback
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FEATURES
28-/56-bit, 50 MIPS digital audio processor
2 ADCs: SNR of 100 dB, THD + N of −83 dB
4 DACs: SNR of 104 dB, THD + N of −90 dB
Complete standalone operation
Self-boot from serial EEPROM
Auxiliary ADC with 4-input mux for analog control
GPIOs for digital controls and outputs
Fully programmable with SigmaStudio graphical tool
28-bit × 28-bit multiplier with 56-bit accumulator for full
double-precision processing
Clock oscillator for generating a master clock from crystal
PLL for generating master clock from 64 × fS, 256 × fS,
384 × fS, or 512 × fS clocks
Flexible serial data input/output ports with I2S-compatible,
left-justified, right-justified, and TDM modes
Sampling rates of up to 192 kHz are supported
On-chip voltage regulator for compatibility with 3.3 V systems
48-lead, plastic LQFP
APPLICATIONS
Multimedia speaker systems
MP3 player speaker docks
Automotive head units
Minicomponent stereos
Digital televisions
Studio monitors
Speaker crossovers
Musical instrument effects processors
In-seat sound systems (aircraft/motor coaches)
GENERAL DESCRIPTION
The ADAU1701 is a complete single-chip audio system with a
28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like
control interfaces. Signal processing includes equalization, cross-
over, bass enhancement, multiband dynamics processing, delay
compensation, speaker compensation, and stereo image widening.
This processing can be used to compensate for real-world
limitations of speakers, amplifiers, and listening environments,
providing dramatic improvements in perceived audio quality.
Its signal processing is comparable to that found in high end
studio equipment. Most processing is done in full 56-bit, double
precision mode, resulting in very good low level signal perfor-
mance. The ADAU1701 is a fully programmable DSP. The easy to
use SigmaStudio™ software allows the user to graphically configure
a custom signal processing flow using blocks such as biquad filters,
dynamics processors, level controls, and GPIO interface controls.
ADAU1701 programs can be loaded on power-up either from a
serial EEPROM through its own self-boot mechanism or from
an external microcontroller. On power-down, the current state
of the parameters can be written back to the EEPROM from the
ADAU1701 to be recalled the next time the program is run.
Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog
input to analog output dynamic. Each ADC has a THD + N of
−83 dB, and each DAC has a THD + N of −90 dB. Digital input
and output ports allow a glueless connection to additional
ADCs and DACs. The ADAU1701 communicates through an
I2C® bus or a 4-wire SPI port.
ADAU1701 Data Sheet
Rev. C | Page 2 of 52
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
Analog Performance .................................................................... 5
Digital Input/Output .................................................................... 6
Power .............................................................................................. 6
Temperature Range ...................................................................... 6
PLL and Oscillator ........................................................................ 6
Regulator ........................................................................................ 7
Digital Timing Specifications ..................................................... 7
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 14
System Block Diagram ................................................................... 15
Theory of Operation ...................................................................... 16
Initialization .................................................................................... 17
Power-Up Sequence ................................................................... 17
Control Registers Setup ............................................................. 17
Recommended Program/Parameter Loading Procedure ..... 17
Power Reduction Modes ............................................................ 17
Using the Oscillator .................................................................... 18
Setting Master Clock/PLL Mode .............................................. 18
Voltage Regulator ....................................................................... 19
Audio ADCs .................................................................................... 20
Audio DACs .................................................................................... 21
Control Ports ................................................................................... 22
I2C Port ........................................................................................ 23
SPI Port ........................................................................................ 26
Self-Boot ...................................................................................... 27
Signal Processing ............................................................................ 29
Numeric Formats ........................................................................ 29
Programming .............................................................................. 29
RAMs and Registers ....................................................................... 30
Address Maps .............................................................................. 30
Parameter RAM .......................................................................... 30
Data RAM ................................................................................... 30
Read/Write Data Formats ......................................................... 30
Control Register Map ..................................................................... 32
Control Register Details ................................................................ 34
2048 to 2055 (0x0800 to 0x0807)—Interface Registers ......... 34
2056 (0x0808)—GPIO Pin Setting Register ........................... 35
2057 to 2060 (0x0809 to 0x080C)—Auxiliary ADC Data
Registers ....................................................................................... 36
2064 to 2068 (0x0810 to 0x0814)—Safeload Data Registers 37
2069 to 2073 (0x0815 to 0x819)—Safeload Address
Registers ....................................................................................... 37
2074 to 2075 (0x081A to 0x081B)—Data Capture Registers 38
2076 (0x081C)—DSP Core Control Register ......................... 39
2078 (0x081E)—Serial Output Control Register ................... 40
2079 (0x081F)—Serial Input Control Register ....................... 41
2080 to 2081 (0x0820 to 0x0821)—Multipurpose Pin
Configuration Registers ............................................................. 42
2082 (0x0822)—Auxiliary ADC and Power Control ............ 43
2084 (0x0824)—Auxiliary ADC Enable .................................. 43
2086 (0x0826)—Oscillator Power-Down ................................ 43
2087 (0x0827)—DAC Setup ...................................................... 44
Multipurpose Pins .......................................................................... 45
Auxiliary ADC ............................................................................ 45
General-Purpose Input/Output Pins ....................................... 45
Serial Data Input/Output Ports ................................................ 45
Layout Recommendations ............................................................. 48
Parts Placement .......................................................................... 48
Grounding ................................................................................... 48
Typical Application Schematics .................................................... 49
Self-Boot Mode ........................................................................... 49
I2C Control .................................................................................. 50
SPI Control .................................................................................. 51
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Data Sheet ADAU1701
Rev. C | Page 3 of 52
REVISION HISTORY
5/16—Rev. B to Rev. C
Changes to Audio DACs Section and Figure 19 ......................... 21
6/11—Rev. A to Rev. B
Deleted Table 2; Renumbered Sequentially ................................... 6
Changes to Table 4 ............................................................................ 6
2/11—Rev. 0 to Rev. A
Moved Figure 1 .................................................................................. 4
Changes to Specifications Section ................................................... 5
Changes to Table 8, Test Conditions/Comments Column .......... 8
Reordered Figures in Digital Timing Diagrams Section ............. 9
Changes to Figure 2 ........................................................................... 9
Changes to Figure 5 and Figure 6 ................................................. 10
Changes to Table 11 ........................................................................ 12
Replaced Figure 8 to Figure 11 ...................................................... 15
Renamed Theory of Operation Section ....................................... 17
Changes to Initialization Section .................................................. 18
Change to Setting the Master Clock/PLL Mode Section ........... 19
Changes to Table 15 ........................................................................ 23
Replaced Figure 22 through Figure 25 ......................................... 26
Changes to EEPROM Format Section .......................................... 28
Deleted Table 20, Renumbered Sequentially ............................... 29
Inserted Figure 28, Renumbered Sequentially ............................ 29
Changes to Control Register Details Section .............................. 35
Changes to Ordering Guide ........................................................... 53
7/07—Revision 0: Initial Version
A» —> , , LH—i_l+z 3-3 {I {a {a {2 E1 *J 9% @355
ADAU1701 Data Sheet
Rev. C | Page 4 of 52
FUNCTIONAL BLOCK DIAGRAM
2
2
GPIO
INPUT/OUTPUT MATRIX
DIGITAL
VDD DIGITAL
GROUNDANALOG
VDD ANALOG
GROUND PLL
MODE PLL LOOP
FILTER CRYSTAL
3.3V
28-/56-BIT, 50MIPS
AUDIO PROCESSOR CORE
40ms DELAY MEMORY
2-CHANNEL
ANALOG
INPUT
1.8V
REGULATOR
STEREO
ADC
FILTA/
ADC_RES
RESET/
MODE
SELECT
CONTROL
INTERFACE
AND
SELFBOOT
8-CH
DIGITAL
INPUT
8-CH
DIGITAL
OUTPUT
8-BIT
AUX
ADC
RESET SELFBOOT DIGITAL IN
OR GPIO AUX ADC
OR GPIO DIGITAL OUT
OR GPIO
I
2
C/SPI
AND WRITEBACK
DAC
DAC 4-CHANNEL
ANALOG
OUTPUT
FILTD/CM
PLL CLOCK
OSCILLATOR
ADAU1701
33322
2
3
3
3
5
06412-001
Figure 1.
Table L
Data Sheet ADAU1701
Rev. C | Page 5 of 52
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted.
ANALOG PERFORMANCE
Specifications are guaranteed at 25°C (ambient).
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC INPUTS
Number of Channels 2 Stereo input
Resolution 24 Bits
Full-Scale Input 100 (283) µA rms (µA p-p) 2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ
internal) series resistor
Signal-to-Noise Ratio
A-Weighted 100 dB
Dynamic Range −60 dB with respect to full-scale analog input
A-Weighted 95 100 dB
Total Harmonic Distortion + Noise 83 dB −3 dB with respect to full-scale analog input
Interchannel Gain Mismatch 25 250 mdB
Crosstalk 82 dB Analog channel-to-channel crosstalk
DC Bias 1.4 1.5 1.6 V
Gain Error −11 +11 %
DAC OUTPUTS
Number of Channels 4 Two stereo output channels
Resolution
Bits
Full-Scale Analog Output 0.9 (2.5) V rms (V p-p)
Signal-to-Noise Ratio
A-Weighted 104 dB
Dynamic Range −60 dB with respect to full-scale analog output
A-Weighted 99 104 dB
Total Harmonic Distortion + Noise −90 dB −1 dB with respect to full-scale analog output
Crosstalk 100 dB Analog channel-to-channel crosstalk
Interchannel Gain Mismatch 25 250 mdB
Gain Error −10 +10 %
DC Bias 1.4 1.5 1.6 V
VOLTAGE REFERENCE
Absolute Voltage (CM) 1.4 1.5 1.6 V
AUXILIARY ADC
Full-Scale Analog Input 2.8 3.0 3.1 V
INL 0.5 LSB
DNL 1.0 LSB
Offset 15 mV
Input Impedance 17.8 30 42
Table 2‘ Table 3‘ Table 4‘
ADAU1701 Data Sheet
Rev. C | Page 6 of 52
DIGITAL INPUT/OUTPUT
Table 2.
Parameter Symbol Min Typ Max1 Unit Test Conditions/Comments
Input Voltage, High
V
IH
2.0
IOVDD
V
Input Voltage, Low VIL 0.8 V
Input Leakage, High IIH 1 µA Excluding MCLKI
Input Leakage, Low IIL 1 µA Excluding MCLKI and bidirectional pins
Bidirectional Pin Pull-Up Current, Low 150 µA
MCLKI Input Leakage, High IIH 3 µA
MCLKI Input Leakage, Low IIL 3 µA
High Level Output Voltage VOH 2.0 V IOH = 2 mA
Low Level Output Voltage VOL 0.8 V IOL = 2 mA
Input Capacitance 5 pF
GPIO Output Drive 2 mA
1 Maximum specifications are measured across a temperature range of 40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
POWER
Table 3.
Parameter
Min
Typ
Max
1
Unit
SUPPLY VOLTAGE
Analog Voltage 3.3 V
Digital Voltage 1.8 V
PLL Voltage 3.3 V
IOVDD Voltage 3.3 V
SUPPLY CURRENT
Analog Current (AVDD and PVDD) 50 85 mA
Digital Current (DVDD) 40 60 mA
Analog Current, Reset 35 55 mA
Digital Current, Reset
1.5
4.5
mA
DISSIPATION
Operation (AVDD, DVDD, PVDD)2 286.5 mW
Reset, All Supplies 118 mW
POWER SUPPLY REJECTION RATIO (PSRR)
1 kHz, 200 mV p-p Signal at AVDD 50 dB
1 Maximum specifications are measured across a temperature range of 40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
2 Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE
Table 4.
Parameter Min Typ Max Unit
Functionality Guaranteed 0 70 °C ambient
PLL AND OSCILLATOR
Table 5. PLL and Oscillator1
Parameter Min Typ Max Unit
PLL Operating Range MCLK_Nom 20% MCLK_Nom + 20% MHz
PLL Lock Time 20 ms
Crystal Oscillator Transconductance (gm) 78 mmho
1 Maximum specifications are measured across a temperature range of 40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
Table 6‘ Regulator Table 7‘ Digital Timing
Data Sheet ADAU1701
Rev. C | Page 7 of 52
REGULATOR
Table 6. Regulator1
Parameter Min Typ Max Unit
DVDD Voltage
1.7
1.8
1.84
V
1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
DIGITAL TIMING SPECIFICATIONS
Table 7. Digital Timing1
Limit
Parameter tMIN tMAX Unit Test Conditions/Comments
MASTER CLOCK
tMP 36 244 ns MCLKI period, 512 × fS mode
48 366 ns MCLKI period, 384 × fS mode
73 488 ns MCLKI period, 256 × fS mode
291 1953 ns MCLKI period, 64 × fS mode
SERIAL PORT
tBIL 40 ns INPUT_BCLK (Pin 9) low pulse width
tBIH 40 ns INPUT_BCLK (Pin 9) high pulse width
t
LIS
10
ns
INPUT_LRCLK (Pin 8) setup; time to INPUT_BCLK rising
tLIH 10 ns INPUT_LRCLK (Pin 8) hold; time from INPUT_BCLK rising
tSIS 10 ns SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) setup; time to INPUT_BCLK (Pin 9)
rising
tSIH 10 ns SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) hold; time from INPUT_BCLK (Pin 9)
rising
tLOS 10 ns OUTPUT_LRCLK (Pin 16) setup in slave mode
tLOH 10 ns OUTPUT_LRCLK (Pin 16) hold in slave mode
tTS 5 ns OUTPUT_BCLK (Pin 11) falling to OUTPUT_LRCLK (Pin 16) timing skew
tSODS 40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in slave mode; time from
OUTPUT_BCLK (Pin 11) falling
tSODM 40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in master mode; time from
OUTPUT_BCLK (Pin 11) falling
SPI PORT
fCCLK 6.25 MHz CCLK (Pin 23) frequency
tCCPL 80 ns CCLK (Pin 23) pulse width low
tCCPH 80 ns CCLK (Pin 23) pulse width high
tCLS 0 ns CLATCH (Pin 21) setup; time to CCLK (Pin 23) rising
tCLH 100 ns CLATCH (Pin 21) hold; time from CCLK (Pin 23) rising
tCLPH 80 ns CLATCH (Pin 21) pulse width high
t
CDS
0
ns
CDATA (Pin 20) setup; time to CCLK (Pin 23) rising
tCDH 80 ns CDATA (Pin 20) hold; time from CCLK (Pin 23) rising
tCOD 101 ns COUT (Pin 22) delay; time from CCLK (Pin 23) falling
I2C PORT
fSCL 400 kHz SCL (Pin 23) frequency
tSCLH 0.6 µs SCL (Pin 23) high
tSCLL 1.3 µs SCL (Pin 23) low
tSCS 0.6 µs Setup time, relevant for repeated start condition
tSCH 0.6 µs Hold time; after this period, the first clock is generated
tDS 100 ns Data setup time
tSCR 300 ns SCL (Pin 23) rise time
tSCF 300 ns SCL (Pin 23) fall time
tSDR 300 ns SDA (Pin 22) rise time
tSDF 300 ns SDA (Pin 22) fall time
t
BFT
0.6
Bus-free time; time between stop and start
V 7 “““ \ / \ X “““ \ / \‘ ‘x “““ \ ‘1: NA fl Ml.
ADAU1701 Data Sheet
Rev. C | Page 8 of 52
Limit
Parameter tMIN t
MAX Unit Test Conditions/Comments
MULTIPURPOSE PINS AND RESET
tGRT 50 ns GPIO (MPx pins) rise time
tGFT 50 ns GPIO (MPx pins) fall time
tGIL 1.5 × 1/fS μs GPIO (MPx pins) input latency; time until high/low value is read by core
tRLPW 20 ns
RESET low pulse width
1 All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 65).
Digital Timing Diagrams
INPUT_BCLK
INPUT_LRCLK
SDATA_INx
LEFT-JUSTIFIED
MODE
LSB
SDATA_INx
I2S MODE
SDATA_INx
RIGHT-JUSTIFIED
MODE
t
BIH
MSB MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LIS
t
SIS
t
SIH
t
SIH
t
SIS
t
SIS
t
SIH
t
SIS
t
SIH
t
LIH
t
BIL
0
6412-002
Figure 2. Serial Input Port Timing
CLATCH
CCLK
CDATA
COUT
t
CLS
t
CDS
t
CDH
t
COD
t
CCPH
t
CCPL
t
CLH
t
CLPH
06412-004
Figure 3. SPI Port Timing
r r { F { E U /—_X:,’f—X—\ I—\ l—\ I— d RESET
Data Sheet ADAU1701
Rev. C | Page 9 of 52
t
SCH
t
SCLH
t
SCR
t
SCLL
t
SCF
t
DS
SDA
SCL
t
SCH
t
BFT
t
SCS
06412-005
Figure 4. I2C Port Timing
OUTPUT_BCLK
OUTPUT_LRCLK
SDATA_OUTx
LEFT-JUSTIFIED
MODE
LSB
SDATA_OUTx
I2S MODE
SDATA_OUTx
RIGHT-JUSTIFIED
MODE
MSB MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tLOS
tSODS
tSODM
tTS
tSODS
tSODM
tSODS
tSODM
06412-003
Figure 5. Serial Output Port Timing
MCLKI
RESET
t
MP
t
RLPW
06412-006
Figure 6. Master Clock and RESET Timing
Table 8‘ Table 9‘ Thermal Resistance A M ESD [electrosmic charge) sensitive deviu. Chavged dams: and mum boards can dxxchavge w‘mm daemon Mmaugh ms pmdun lemmas pmemed or pvopne‘ary pvmemon cwwmy, damage may cum on dewces Sumened m m» energy ESD Therefore, pvopev ESD premmions shou‘d be men In avmd pymymam degvadamm m loss of lundlunahw
ADAU1701 Data Sheet
Rev. C | Page 10 of 52
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
DVDD to GND 0 V to 2.2 V
AVDD to GND
0 V to 4.0 V
IOVDD to GND 0 V to 4.0 V
Digital Inputs DGND − 0.3 V, IOVDD + 0.3 V
Maximum Junction Temperature 135°C
Temperature Range
Storage −65°C to +150°C
Operating 0°C to +70°C
Soldering (10 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 9. Thermal Resistance
Package Type θJA θJC Unit
48-Lead LQFP 72 19.5 °C/W
ESD CAUTION
33333333333] RESET
Data Sheet ADAU1701
Rev. C | Page 11 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
AVDD
PLL_LF
PVDD
PGND
MCLKI
OSCO
RSVD
MP2
MP3
MP8
MP9
DGND
DVDD
MP7
MP6
MP10
VDRIVE
IOVDD
MP11
ADDR1/CDATA/WB
CLATCH/WP
SDA/COUT
SCL/CCLK
DVDD
AGND
ADC0
ADC_RES
ADC1
RESET
SELFBOOT
ADDR0
MP4
MP5
MP1
MP0
DGND
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
AVDD
FILTA
VOUT0
VOUT1
VOUT2
VOUT3
AGND
FILTD
CM
PLL_MODE1
PLL_MODE0
AGND
ADAU1701
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
06412-007
Figure 7. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1, 37, 42 AGND PWR Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple AGND to an AVDD pin with a 100 nF capacitor.
2
ADC0
A_IN
Analog Audio Input 0. Full-scale 100 μA rms input. Current input allows input voltage level
to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input. See
the Audio ADCs section for details.
3 ADC_RES A_IN ADC Reference Current. Set the full-scale current of the ADCs with an external 18 kΩ resistor
connected between this pin and ground. See the Audio ADCs section for details.
4 ADC1 A_IN Analog Audio Input 1. Full-scale 100 μA rms input. Current input allows the input voltage
level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input.
5 RESET D_IN Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1701 exits
reset on a low-to-high edge. For more information about initialization, see the Power-Up
Sequence section for details.
6 SELFBOOT D_IN Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting
this pin high initiates a self-boot operation when the ADAU1701 is brought out of a reset. This
pin can be tied directly to the control voltage or pulled up/down with a resistor. See the
Self-Boot section for details.
7 ADDR0 D_IN I2C and SPI Address 0. In combination with ADDR1 function on Pin 20, this pin allows up to
four ADAU1701 devices to be used on the same I2C bus and up to two ICs to be used with a
common SPI CLATCH signal. See the I2C Port section for details.
8
MP4
D_IO
Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). See the Multipurpose Pins
section for more details.
9 MP5 D_IO Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). See the Multipurpose Pins
section for more details.
10 MP1 D_IO Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0). See the Multipurpose Pins
section for more details.
11 MP0 D_IO Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1). See the Multipurpose Pins
section for more details.
12, 25 DGND PWR Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple DGND to a DVDD pin with a 100 nF capacitor.
13, 24 DVDD PWR 1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V supply
with the on-board 1.8 V regulator. Decouple DVDD to DGND with a 100 nF capacitor.
ADAU1701 Data Sheet
Rev. C | Page 12 of 52
Pin No. Mnemonic Type 1 Description
14 MP7 D_IO Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1). See the Multipurpose Pins
section for more details.
15 MP6 D_IO Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0). See the
Multipurpose Pins section for more details.
16
MP10
D_IO
Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK). See the Multipurpose
Pins section for more details.
17 VDRIVE A_OUT Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is driven
from VDRIVE. See the Voltage Regulator section for details.
18 IOVDD PWR Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage
that should be seen on the digital input pins. This pin is also the supply for the digital
output signals on the control port and MP pins. Always set IOVDD to 3.3 V. The current draw
of this pin is variable because it is dependent on the loads of the digital outputs.
19 MP11 D_IO Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins
section for more details.
20 ADDR1/CDATA/WB D_IN I2C Address 1/SPI Data Input/EEPROM Write Back Trigger. This is a multifunction pin as
follows:
ADDR1: I2C Address 1. In combination with ADDR0, this sets the I2C address of the IC so that
four ADAU1701 devices can be used on the same I2C bus. See the I2C Port section for
details.
CDATA: SPI Data Input. See the SPI Port section for details.
WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the EEPROM messages)
edge on this pin triggers a writeback of the interface registers to the external EEPROM. This
function can be used to save parameter data on power-down. See the Self-Boot section for
details.
21 CLATCH/WP D_IO SPI Latch Signal/Self-Boot EEPROM Write Protect. This is a multifunction pin as follows:
CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of cycles on the CCLK
pin to complete, depending on the address and read/write bit that are sent at the beginning
of the SPI transaction. See the SPI Port section for details.
WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output when in self-boot
mode. The ADAU1701 pulls this low to enable writes to an external EEPROM. This pin
should be pulled high to 3.3 V. See the Self-Boot section for details.
22 SDA/COUT D_IO I2C Data/SPI Data Output. This is a multifunction pin, as follows:
SDA: I2C Data. This pin is a bidirectional open-collector. The line connected to this pin
should have a 2.2 kΩ pull-up resistor. See the I2C Port section for details.
COUT: This SPI data output is used for reading back registers and memory locations. It is
three-stated when an SPI read is not active. See the SPI Port section for details.
23 SCL/CCLK D_IO I2C Clock/SPI Clock. This is a dual function pin, as follows:
SCL: I2C Clock. This pin is always an open-collector input when in I2C control mode. In self-
boot mode, this pin is an open-collector output (I2C master). The line connected to this pin
should have a 2.2 kΩ pull-up resistor. See the I2C Port section for details.
CCLK: SPI Clock. This pin can either run continuously or be gated off between SPI
transactions. See the SPI Port section for details.
26 MP9 D_IO/A_IO Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0. See
the Multipurpose Pins section for more details.
27 MP8 D_IO/A_IO Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3. See
the Multipurpose Pins section for more details.
28 MP3 D_IO/A_IO Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2. See the
Multipurpose Pins section for more details.
29
MP2
D_IO/A_IO
Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1. See the
Multipurpose Pins section for more details.
30 RSVD Reserved. Tie to ground, either directly or through a pull-down resistor.
31 OSCO D_OUT Crystal Oscillator Circuit Output. Connect a 100 Ω damping resistor between this pin and
the crystal. Do not use this output to directly drive a clock to another IC. If the crystal
oscillator is not used, this pin can be left disconnected. See the Using the Oscillator section
for details.
32 MCLKI D_IN Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or be the input
from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for details.
Data Sheet ADAU1701
Rev. C | Page 13 of 52
Pin No. Mnemonic Type 1 Description
33 PGND PWR PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor.
34 PVDD PWR 3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to
PGND by using a 100 nF capacitor.
35
PLL_LF
A_OUT
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
36, 48 AVDD PWR 3.3 V Analog Supply. Decouple this pin to AGND by using a 100 nF capacitor.
38, 39 PLL_MODE0,
PLL_MODE1
D_IN PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master
clock PLL. See the Setting Master Clock/PLL Mode section for more details.
40 CM A_OUT 1.5 V Common-Mode Reference. Connect a 47 μF decoupling capacitor between this pin and
ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not
critical. This pin can be used to bias external analog circuits, as long as those circuits are not
drawing current from the pin (such as when CM is connected to the noninverting input of
an op amp).
41 FILTD A_OUT DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The
capacitor material is not critical. The voltage on this pin is 1.5 V.
43 to 46 VOUT3 A_OUT VOUT DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
44 VOUT2 A_OUT VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
45 VOUT1 A_OUT VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
46 VOUT0 A_OUT VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
47 FILTA A_OUT ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and
ground. The capacitor material is not critical. The voltage on this pin is 1.5 V.
1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
input/output.
ADAU1701 Data Sheet
Rev. C | Page 14 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.10
0.15
0
–0.10
0.05
–0.05
–0.15
–0.20 0246810 12 14 16 18 20 22
GAIN (dB)
FREQUENCY (kHz)
f
S
= 48kHz
06412-008
Figure 8. ADC Pass-Band Filter Response
025 30 35 40201510545
GAIN (dB)
FREQUENCY (kHz)
10
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
f
S
= 48kHz
06412-009
Figure 9. ADC Stop-Band Filter Response
0.10
–0.10
0.08
–0.08
0
0.02
–0.02
0.04
–0.04
0.06
–0.06
0510 15 20
GAIN (dB)
FREQUENCY (kHz)
f
S
= 48kHz
06412-010
Figure 10. DAC Pass-Band Filter Response
10
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 2 4 6 8 10 12 14 16 18 20
GAIN (dB)
FREQUENCY (kHz)
f
S
= 48kHz
06412-011
Figure 11. DAC Stop-Band Filter Response
Data Sheet ADAU1701
Rev. C | Page 15 of 52
SYSTEM BLOCK DIAGRAM
22pF
22pF
ADAU1701
ADCs DACs
VOUT0
VOUT1
VOUT2
VOUT3
ADC0
IOVDD PVDD AVDD DVDD VDRIVE
ADC1
ADC_RES
FILTA
FILTD
CM
ADDR0
ADDR1/CDATA/WB
CLATCH/WP
SDA/COUT
SCL/CCLK
SELFBOOT
RESET
RSVD
EEPROM,
MICROCONTROLLER,
AND/OR SELFBOOT
LOGIC
AGND DGND PGND
OSCO
MCLKI
PLL_MODE1
PLL_MODE0
PLL_LF
MP11
MP10
MP9
MP8
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
RESET LOGIC
100nF10µF
100nF10µF +
+
DAC OUTPUT FILTERS
(ACTIVE OR PASSIVE)
MULTIPURPOSE
PIN INTERFACES
100nF
10µF
18kΩ
18kΩ
18kΩ
AUDIO ADC
INPUT SIGNALS
PLL
SETTINGS
3.3V
3MHz TO 25MHz
56nF3.3nF
475
100Ω
3.3V TO 1.8V
REGULATOR
CIRCUIT
3.3V
100nF
100nF
100nF
+
100nF
10µF
+
10µF
+
06412-012
Figure 12. System Block Diagram
ADAU1701 Data Sheet
Rev. C | Page 16 of 52
THEORY OF OPERATION
The core of the ADAU1701 is a 28-bit DSP (56-bit with double-
precision processing) optimized for audio processing. The
program and parameter RAMs can be loaded with a custom
audio processing signal flow built by using SigmaStudio graphical
programming software from Analog Devices, Inc. The values
stored in the parameter RAM control individual signal processing
blocks, such as equalization filters, dynamics processors, audio
delays, and mixer levels. A safeload feature allows for transparent
parameter updates and prevents clicks in the output signals.
The program RAM, parameter RAM, and register contents can
be saved in an external EEPROM, from which the ADAU1701
can self-boot on startup. In this standalone mode, parameters
can be controlled through the on-board multipurpose pins. The
ADAU1701 can accept controls from switches, potentiometers,
rotary encoders, and IR receivers. Parameters such as volume
and tone settings can be saved to the EEPROM on power-down
and recalled again on power-up.
The ADAU1701 can operate with digital or analog inputs and
outputs, or a mix of both. The stereo ADC and four DACs each
have an SNR of at least +100 dB and a THD + N of at least 83 dB.
The 8-channel, flexible serial data input/output ports allow glueless
interconnection to a variety of ADCs, DACs, general-purpose
DSPs, S/PDIF receivers and transmitters, and sample rate con-
verters. The serial ports of the ADAU1701 can be configured in
I2S, left-justified, right-justified, or TDM serial port-compatible
modes.
Twelve multipurpose (MP) pins allow the ADAU1701 to receive
external control signals as input and to output flags or controls
to other devices in the system. The MP pins can be configured
as digital I/Os, inputs to the 4-channel auxiliary ADC, or serial data
I/O ports. As inputs, they can be connected to buttons, switches,
rotary encoders, potentiometers, IR receivers, or other external
circuitry to control the internal signal processing program. When
configured as outputs, these pins can be used to drive LEDs,
control other ICs, or connect to other external circuitry in an
application.
The ADAU1701 has a sophisticated control port that supports
complete read/write capability of all memory locations. Control
registers are provided to offer complete control of the configu-
ration and serial modes of the chip. The ADAU1701 can be
configured for either SPI or I2C control, or can self-boot from
an external EEPROM.
An on-board oscillator can be connected to an external crystal
to generate the master clock. In addition, a master clock phase-
locked loop (PLL) allows the ADAU1701to be clocked from a
variety of different clock speeds. The PLL can accept inputs of
64 × fS, 256 × fS, 384 × fS, or 512 × fS to generate the internal
master clock of the core.
The SigmaStudio software is used to program and control the
SigmaDSP® through the control port. Along with designing and
tuning a signal flow, the tools can be used to configure all of the
DSP registers and burn a new program into the external EEPROM.
The SigmaStudio graphical interface allows anyone with digital
or analog audio processing knowledge to easily design a DSP
signal flow and port it to a target application. At the same time,
it provides enough flexibility and programmability for an expe-
rienced DSP programmer to have in-depth control of the design.
In SigmaStudio, the user can connect graphical blocks (such as
biquad filters, dynamics processors, mixers, and delays), compile
the design, and load the program and parameter files into the
ADAU1701memory through the control port. Signal processing
blocks available in the provided libraries include
Single- and double-precision biquad filters
Processors with peak or rms detection for monochannel
and multichannel dynamics
Mixers and splitters
Tone and noise generators
Fixed and variable gain
Loudness
Delay
Stereo enhancement
Dynamic bass boost
Noise and tone sources
FIR filters
Level detectors
GPIO control and conditioning
Additional processing blocks are always being developed.
Analog Devices also provides proprietary and third-party
algorithms for applications such as matrix decoding, bass
enhancement, and surround virtualizers. Contact Analog
Devices for information about licensing these algorithms.
The ADAU1701 operates from a 1.8 V digital power supply
and a 3.3 V analog supply. An on-board voltage regulator can
be used to operate the chip from a single 3.3 V supply. It is
fabricated on a single monolithic, integrated circuit and is
packaged in a 48-lead LQFP for operation over the 0°C to
+70°C temperature range.
Data Sheet ADAU1701
Rev. C | Page 17 of 52
INITIALIZATION
This section details the procedure for properly setting up the
ADAU1701. The following five-step sequence provides an
overview of how to initialize the IC:
1. Apply power to ADAU1701.
2. Wait for PLL to lock.
3. Load SigmaDSP program and parameters.
4. Set up registers (including multipurpose pins and digital
interfaces).
5. Turn off the default muting of the converters, clear the
data registers, and initialize the DAC setup register (see
the Control Registers Setup section for specific settings).
To only test analog audio pass-through (ADCs to DACs), skip
Step 3 and Step 4 and use the default internal program.
POWER-UP SEQUENCE
The ADAU1701 has a built-in power-up sequence that
initializes the contents of all internal RAMs on power-up or
when the device is brought out of a reset. On the positive edge
of RESET, the contents of the internal program boot ROM are
copied to the internal program RAM memory, the parameter
RAM is filled with values (all 0s) from its associated boot ROM,
and all registers are initialized to 0s. The default boot ROM
program copies audio from the inputs to the outputs without
processing it (see Figure 13). In this program, serial digital
Input 0 and Input 1 are output on DAC0 and DAC1 and serial
digital Output 0 and Output 1. ADC0 and ADC1 are output on
DAC2 and DAC3. The data memories are also zeroed at power-
up. New values should not be written to the control port until
the initialization is complete.
Table 11. Power-Up Time
MCLKI Input
Init.
Time
Max Program/
Parameter/Register
Boot Time (I2C) To t al
3.072 MHz (64 × fS) 85 ms 175 ms 260 ms
11.289 MHz (256 × fS) 23 ms 175 ms 198 ms
12.288 MHz (256 × fS) 21 ms 175 ms 196 ms
18.432 MHz (384 × fS) 16 ms 175 ms 191 ms
24.576 MHz (512 × fS) 11 ms 175 ms 186 ms
The PLL start-up time lasts for 218 cycles of the clock on the
MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz
(512 × fS) input clock to 85.3 ms for a 3.072 MHz (64 × fS) input
clock and is measured from the rising edge of RESET. Following
the PLL startup, the duration of the ADAU1701 boot cycle is about
42 μs for a fS of 48 kHz. The user should avoid writing to or reading
from the ADAU1701 during this start-up time. For an MCLK
input of 12.288 MHz, the full initialization sequence (PLL
startup plus boot cycle) is approximately 21 ms. As the device
comes out of a reset, the clock mode is immediately set by the
PLL_MODE0 and PLL_MODE1 pins. The reset is synchronized
to the falling edge of the internal clock.
Table 11 lists typical times to boot the ADAU1701 into an
operational state of an application, assuming a 400 kHz I2C
clock loading a full program, parameter set, and all registers
(about 8.5 kB). In reality, most applications do not fill the RAMs
and therefore boot time (Column 3 of Table 11) is less.
CONTROL REGISTERS SETUP
The following registers must be set as described in this section
to initialize the ADAU1701. These settings are the basic
minimum settings needed to operate the IC with an analog
input/output of 48 kHz. More registers may need to be set,
depending on the application. See the RAMs and Registers
section for additional settings.
DSP Core Control Register (Address 2076)
Set Bits[4:2] (ADM, DAM, and CR) each to 1.
DAC Setup Register (Address 2087)
Set Bits[0:1] (DS[1:0]) to 01.
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURE
When writing large amounts of data to the program or para-
meter RAM in direct write mode, the processor core should
be disabled to prevent unpleasant noises from appearing in
the audio output.
1. Set Bit 3 and Bit 4 (active low) of the core control register
to 1 to mute the ADCs and DACs. This begins a volume
ramp-down.
2. Set Bit 2 (active low) of the core control register to 1. This
zeroes the SigmaDSP accumulators, the data output registers,
and the data input registers.
3. Fill the program RAM using burst mode writes.
4. Fill the parameter RAM using burst mode writes.
5. Deassert Bit 2 to Bit 4 of the core control register.
ADC0
DAC1
DAC0
DAC2
DAC3
ADC1
SDATA_IN0 SDATA_OUT0
06412-013
Figure 13. Default Program Signal Flow
POWER REDUCTION MODES
Sections of theADAU1701 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
DACs, and voltage reference.
The individual analog sections can be turned off by writing to
the auxiliary ADC and power control register. By default, the
ADCs, DACs, and reference are enabled (all bits set to 0). Each
of these can be turned off by writing a 1 to the appropriate bits
1mm Table 12. PLL Modes C1 x C2 C1 C2 signals. 11.: mt r ADAUI7D1 _(J—
ADAU1701 Data Sheet
Rev. C | Page 18 of 52
in this register. The ADC power-down mode powers down both
ADCs, and each DAC can be powered down individually. The
current savings is about 15 mA when the ADCs are powered
down and about 4 mA for each DAC that is powered down.
The voltage reference, which is supplied to both the ADCs
and DACs, should only be powered down if all ADCs and
DACs are powered down. The reference is powered down
by setting both Bit 6 and Bit 7 of the control register.
USING THE OSCILLATOR
The ADAU1701can use an on-board oscillator to generate its
master clock. The oscillator is designed to work with a 256 × fS
master clock, which is 12.288 MHz for a fS of 48 kHz and
11.2896 MHz for a fS of 44.1 kHz. The crystal in the oscillator
circuit should be an AT-cut, parallel resonator operating at its
fundamental frequency. Figure 14 shows the external circuit
recommended for proper operation.
C1 100Ω
MCLKI
OSCO
C2
ADAU1701
06412-014
Figure 14. Crystal Oscillator Circuit
The 100 Ω damping resistor on OSCO gives the oscillator a
voltage swing of approximately 2.2 V. The crystal shunt capaci-
tance should be 7 pF. Its load capacitance should be about 18 pF,
although the circuit supports values of up to 25 pF. The necessary
values of the C1 and C2 load capacitors can be calculated from
the crystal load capacitance as follows:
stray
LC
C2C1
C2C1
C+
+
×
=
where Cstray is the stray capacitance in the circuit and is usually
assumed to be approximately 2 pF to 5 pF.
OSCO should not be used to directly drive the crystal signal to
another IC. This signal is an analog sine wave, and it is not appro-
priate to use it to drive a digital input. There are two options for
using the ADAU1701 to provide a master clock to other ICs in
the system. The first, and less recommended, method is to use a
high impedance input digital buffer on the OSCO signal. If this
is done, minimize the trace length to the buffer input. The second
method is to use a clock from the serial output port. Pin MP11 can
be set as an output (master) clock divided down from the internal
core clock. If this pin is set to serial output port (OUTPUT_BCLK)
mode in the multipurpose pin configuration register (2081) and
the port is set to master in the serial output control register (2078),
the desired output frequency can also be set in the serial output
control register with Bits[OBF<1:0>] (see Table 48).
If the oscillator is not utilized in the design, it can be powered
down to save power. This can be done if a system master clock
is already available in the system. By default, the oscillator is
powered on. The oscillator powers down when a 1 is written to
the OPD bit of the oscillator power-down register (see Table 59).
SETTING MASTER CLOCK/PLL MODE
The MCLKI input of theADAU1701feeds a PLL, which generates
the 50 MIPS SigmaDSP core clock. In normal operation, the
input to MCLKI must be one of the following: 64 × fS, 256 × fS,
384 × fS, or 512 × fS, where fS is the input sampling rate. The
mode is set on PLL_MODE0 and PLL_MODE1 as described in
Table 12. If the ADAU1701 is set to receive double-rate signals
(by reducing the number of program steps per sample by a factor
of 2 using the core control register), the master clock frequency
must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1701
is set to receive quad-rate signals (by reducing the number of
program steps per sample by a factor of 4 using the core control
register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS,
or 128 × fS. On power-up, a clock signal must be present on the
MCLKI pin so that the ADAU1701can complete its
initialization routine.
Table 12. PLL Modes
MCLKI Input PLL_MODE0 PLL_MODE1
64 × fS 0 0
256 × fS 0 1
384 × fS 1 0
512 × fS 1 1
The clock mode should not be changed without also resetting
the ADAU1701. If the mode is changed during operation, a
click or pop can result in the output signals. The state of the
PLL_MODEx pins should be changed while RESET is held low.
The PLL loop filter should be connected to the PLL_LF pin. This
filter, shown in Figure 15, includes three passive components
two capacitors and a resistor. The values of these components
do not need to be exact; the tolerance can be up to 10% for the
resistor and up to 20% for the capacitors. The 3.3 V signal shown in
Figure 15 can be connected to the AVDD supply of the chip.
ADAU1701
3.3V
475Ω
PLL_LF
56nF3.3nF
06412-015
Figure 15. PLL Loop Filter
Data Sheet ADAU1701
Rev. C | Page 19 of 52
VOLTAGE REGULATOR
The digital voltage of the ADAU1701 must be set to 1.8 V. The
chip includes an on-board voltage regulator that allows the
device to be used in systems without an available 1.8 V supply
but with an available 3.3 V supply. The only external components
needed in such instances are a PNP transistor, a resistor, and a
few bypass capacitors. Only one pin, VDRIVE, is necessary to
support the regulator.
The recommended design for the voltage regulator is shown
in Figure 16. The 10 µF and 100 nF capacitors shown in this
configuration are recommended for bypassing, but are not
necessary for operation. Each DVDD pin should have its own
100 nF bypass capacitor, but only one bulk capacitor (10 µF to
47 µF) is needed for both DVDD pins. With this configuration,
3.3 V is the main system voltage; 1.8 V is generated at the
transistor’s collector, which is connected to the DVDD pins.
VDRIVE is connected to the base of the PNP transistor. If the
regulator is not used in the design, VDRIVE can be tied to ground.
Two specifications must be considered when choosing a regulator
transistor: The transistors current amplification factor (hFE or
beta) should be at least 100, and the transistor’s collector must
be able to dissipate the heat generated when regulating from
3.3 V to 1.8 V. The maximum digital current drawn from the
ADAU1701 is 60 mA. The equation to determine the minimum
power dissipation of the transistor is as follows:
(3.3 V 1.8 V) × 60 mA = 90 mW
There are many transistors, such as the FZT953 from Zetex
Semiconductors, with these specifications available in small
SOT-23 or SOT-223 packages.
3.3V
1kΩ
VDRIVE
DVDD
10µF
100nF
ADAU1701
+
06412-016
Figure 16. Voltage Regulator Configuration
ADAU1701 Data Sheet
Rev. C | Page 20 of 52
AUDIO ADCs
The ADAU1701 has two Σ-Δ ADCs. The signal-to-noise ratio
(SNR) of the ADCs is 100 dB, and the THD + N is −83 dB.
The stereo audio ADCs are current input; therefore, a voltage-
to-current resistor is required on the inputs. This means that
the voltage level of the input signals to the system can be set to
any level; only the input resistors need to be scaled to provide
the proper full-scale current input. The ADC0 and ADC1 input
pins, as well as ADC_RES, have an internal 2 kΩ resistor for
ESD protection. The voltage seen directly on the ADC input
pins is the 1.5 V common mode.
The external resistor connected to ADC_RES sets the full-scale
current input of the ADCs. The full range of the ADC inputs is
100 µA rms with an external 18 kΩ resistor on ADC_RES (20 kΩ
total, because it is in series with the internal 2 kΩ). The only
reason to change the ADC_RES resistor is if a sampling rate
other than 48 kHz is used.
The voltage-to-current resistors connected to ADC0/ADC1 set
the full-scale voltage input of the ADCs. With a full-scale current
input of 100 µA rms, a 2.0 V rms signal with an external 18 kΩ
resistor (in series with the 2 kΩ internal resistor) results in an
input using the full range of the ADC. The matching of these
resistors to the ADC_RES resistor is important to the operation
of the ADCs. For these three resistors, a 1% tolerance is
recommended.
Either the ADC0 and/or ADC1 input pins can be left
unconnected if that channel of the ADC is unused.
These calculations of resistor values assume a 48 kHz sample
rate. The recommended input and current setting resistors
scale linearly with the sample rate because the ADCs have a
switched-capacitor input. The total value (2 kΩ internal plus
external resistor) of the ADC_RES resistor with sample rate
fS_NEW can be calculated as follows:
NEWS
total
f
R
_
000,
48
20 ×=
The values of the resistors (internal plus external) in series with
the ADC0 and ADC1 pins can be calculated as follows:
NEWS
TotalInput f
VoltageInputrmsR
_
000,48
10)( ××=
Table 13 lists the external and total resistor values for common
signal input levels at a 48 kHz sampling rate. A full-scale rms
input voltage of 0.9 V is shown in the table because a full-scale
signal at this input level is equal to a full-scale output on the DACs.
Table 13. ADC Input Resistor Values
Full-Scale
RMS Input
Voltage (V)
ADC_RES
Value (kΩ)
ADC0/ADC1
Resistor
Value (kΩ)
Total ADC0/ADC1
Input Resistance
(External +
Internal) (kΩ)
0.9 18 7 9
1.0
18
8
10
2.0 18 18 20
Figure 17 shows a typical configuration of the ADC inputs for
a 2.0 V rms input signal for a fS of 48 kHz. The 47 μF capacitors are
used to ac-couple the signals so that the inputs are biased at 1.5 V.
ADC1
ADC0
ADC_RES
18k
47µF
18k
47µF
18k
ADAU1701
06412-017
Figure 17. Audio ADC Input Configuration
D—<—wv—l—d 4|="" i="">
Data Sheet ADAU1701
Rev. C | Page 21 of 52
AUDIO DACs
The ADAU1701 includes four ΣDACs. The SNR of the DAC
is 104 dB, and the THD + N is −90 dB. A full-scale output on
the DACs is 0.9 V rms (2.5 V p-p).
The DACs are in an inverting configuration. If a signal inversion
from input to output is undesirable, it can be reversed either by
using an inverting configuration for the output filter or by simply
inverting the signal in the SigmaDSP program flow.
The DAC outputs can be filtered with either an active or a
passive reconstruction filter. A single-pole, passive, low-pass
filter with a 50 kHz corner frequency, as shown in Figure 18,
is sufficient to filter the DAC out-of-band noise, although an
active filter may provide better audio performance. Figure 19
shows a triple-pole, active, low-pass filter that provides a steeper
roll-off and better stop band attenuation than the passive filter.
In this configuration, the V+ and V− pins of the AD8606 op
amp are set to AVDD and ground, respectively.
To properly initialize the DACs, the DS[1:0] bits in the DAC
setup register (Address 2087) should be set to 01.
47µF
+
560
DAC_OUT
5.6nF
FILTER_OUT
06412-018
Figure 18. Passive DAC Output Filter
47µF
+
604
DAC_OUT
49.9k
3.3nF
FILTER_OUT
4.75k
4.75k
150pF
AD8606
C8
470pF
06412-019
Figure 19. Active DAC Output Filter
unu R/ W
ADAU1701 Data Sheet
Rev. C | Page 22 of 52
CONTROL PORTS
The ADAU1701 can operate in one of three control modes:
I2C control
SPI control
Self-boot (no external controller)
The ADAU1701has both a 4-wire SPI control port and a 2-wire
I2C bus control port. Each can be used to set the RAMs and
registers. When the SELFBOOT pin is low at power-up, the part
defaults to I2C mode but can be put into SPI control mode by
pulling the CLATCH/WP pin low three times. When the SELF-
BOOT pin is set high at power-up, the ADAU1701 loads its
program, parameters, and register settings from an external
EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory and registers. Most signal processing
parameters are controlled by writing new values to the param-
eter RAM using the control port. Other functions, such as mute
and input/output mode control, are programmed by writing to
the registers.
All addresses can be accessed in a single-address mode or a
burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1701. This
subaddress must be two bytes because the memory locations
within the ADAU1701 are directly addressable and their sizes
exceed the range of single-byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in Table 21 to Table 30.
TheADAU1701 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at startup or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on the fly, the
SigmaDSP provides the safeload registers. The safeload registers
can be used to buffer a full set of parameters (for example, the
five coefficients of a biquad) and then transfer these parameters
into the active program within one audio frame. The safeload
mode uses internal logic to prevent contention between the
DSP core and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 14 details these
multiple functions.
Table 14. Control Port Pins and SELFBOOT Pin Functions
Pin I2C Mode SPI Mode Self-Boot
SCL/CCLK SCL—input CCLKinput SCL—output
SDA/COUT SDA—open-collector output COUToutput SDA—open-collector output
ADDR1/CDATA/WB ADDR1input CDATAinput WBwriteback trigger
CLATCH/WP Unused inputtie to ground or IOVDD CLATCHinput WPEEPROM write protect, open-collector output
ADDR0 ADDR0input ADDR0input Unused inputtie to ground or IOVDD
The {n by_le write (ww R/W 5‘ mm Lh W mu W
Data Sheet ADAU1701
Rev. C | Page 23 of 52
I2C PORT
The ADAU1701supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1701and the system I2C master controller. In
I2C mode, theADAU1701 is always a slave on the bus, meaning
it cannot initiate a data transfer. Each slave device is recognized
by a unique address. The address byte format is shown in Table
15. The ADAU1701 slave addresses are set with the ADDR0 and
ADDR1 pins. The address resides in the first seven bits of the
I2C write. The LSB of this byte sets either a read or write
operation. Logic Level 1 corresponds to a read operation, and
Logic Level 0 corresponds to a write operation. Bit 5 and Bit 6
of the address are set by tying the ADDRx pins of the
ADAU1701 to Logic Level 0 or Logic Level 1. The full byte
addresses, including the pin settings and read/write (R/W) bit,
are shown in Table 16.
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless
a stop condition is encountered. The registers and RAMs in the
ADAU1701 range in width from one to five bytes, so the auto-
increment feature knows the mapping between subaddresses and
the word length of the destination register (or memory location).
A data transfer is always terminated by a stop condition.
Both SDA and SCL should have 2.2 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than IOVDD (3.3 V).
Table 15. ADAU1701 I2C Address Byte Format
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
0 1 1 0 1 ADDR1 ADDR0 R/W
Table 16. ADAU1701 I2C Addresses
ADDR1 ADDR0 R/W Slave Address
0 0 0 0x68
0 0 1 0x69
0 1 0 0x6A
0 1 1 0x6B
1 0 0 0x6C
1 0 1 0x6D
1 1 0 0x6E
1
1
1
0x6F
Addressing
Initially, each device on the I2C bus is in an idle state monitoring
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address/data stream
follows. All devices on the bus respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/W bit)
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is known as an acknowledge bit. All other
devices withdraw from the bus at this point and return to the
idle condition. The R/W bit determines the direction of the
data. A Logic 0 on the LSB of the first byte means the master
writes information to the peripheral, whereas a Logic 1 means
the master reads information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop condi-
tion occurs when SDA transitions from low to high while SCL
is held high. Figure 20 shows the timing of an I2C write, and
Figure 21 shows an I2C read.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, theADAU1701 immediately
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1701 does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU1701
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. On the other hand, if the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the ADAU1701, and the part returns
to the idle condition.
ADAU1701 Data Sheet
Rev. C | Page 24 of 52
R/W
0
SCL
SDA
SDA
(CONTINUED)
SCL
(CONTINUED)
11 0 ADDR
SEL
10
START BY
MASTER FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
DATA BYTE 1
ACK BY
ADAU1701
ACK BY
ADAU1701
ACK BY
ADAU1701
ACK BY
ADAU1701
STOP BY
MASTER
06412-020
Figure 20. I2C Write to ADAU1701 Clocking
R/W
SCL
SDA 0 0 011 1
SDA
(CONTINUED)
SCL
(CONTINUED)
SDA
(CONTINUED)
SCL
(CONTINUED)
ADR
SEL
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
FRAME 6
READ DATA BYTE 2
FRAME 5
READ DATA BYTE 1
ACK BY
ADAU1701
ACK BY
ADAU1701
ACK BY
ADAU1701
ACK BY
ADAU1701
STOP BY
MASTER
ACK BY
MASTER
ACK BY
MASTER
REPEATED
START BY MASTER
R/W
ADDR
SEL
06412-021
Figure 21. I2C Read from ADAU1701 Clocking
AD RIW WW
Data Sheet ADAU1701
Rev. C | Page 25 of 52
I2C Read and Write Operations
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1701 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1701 knows to increment
its subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in
Figure 24. Note that the first R/W bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the
ADAU1701acknowledges the receipt of the subaddress, the
master must issue a repeated start command followed by the
chip address byte with the R/W set to 1 (read). This causes the
ADAU1701 SDA to reverse and begin driving data back to the
master. The master then responds every ninth pulse with an
acknowledge pulse to the ADAU1701.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1701 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other addresses
may have word lengths ranging from one to five bytes. The
ADAU1701 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
SAS AS AS AS
SUBADDRESS
LOW DATA BYTE 1 DATA BYTE 2 AS PDATA BYTE N
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
06412-022
Figure 22. Single Word I2C Write Format
SAS AS AS AS
SUBADDRESS
LOW
DATA-
WORD 1,
BYTE 1
DATA-
WORD 1,
BYTE 2
DATA-
WORD 2,
BYTE 1
DATA-
WORD 2,
BYTE 2
AS ASAS P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
06412-023
Figure 23. Burst Mode I2C Write Format
SAS AS AS S
SUBADDRESS
LOW AM AMAS DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE N P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
06412-024
Figure 24. Single-Word I2C Read Format
SAS AS AS S
SUBADDRESS
LOW AMAS
DATA-
WORD 1,
BYTE 1
AM
DATA-
WORD 1,
BYTE 2
P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
0
6412-025
Figure 25. Burst Mode I2C Read Format
% Table I7. ADAU1701 SP1 Address Byte Formal R/W E \ l‘hc fimy R/ W H11: R/W \\\N ,, . ,, //// WWWW / x ’ x 5’ x ; \ WWWUWWW / =; x f x >o<><><\>
ADAU1701 Data Sheet
Rev. C | Page 26 of 52
SPI PORT
By default, the ADAU1701 is in I2C mode, but it can be put into
SPI control mode by pulling CLATCH/WP low three times. The
SPI port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals, and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA during a low-to-high transition. COUT data is shifted
out of theADAU1701 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on the
CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 18. A timing diagram is shown in Figure 3. All
data should be written MSB first. The ADAU1701 cannot be
taken out of SPI mode without a full reset.
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1701s to share a CLATCH signal, yet still operate
independently. When ADDR0 is low, the chip address is 0000000;
when it is high, the address is 0000001 (see Table 17). The LSB
of this first byte determines whether the SPI transaction is a
read (Logic Level 1) or a write (Logic Level 0).
Table 17. ADAU1701 SPI Address Byte Format
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
0 0 0 0 0 0 ADDR0 R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register. The MSBs of the subaddress
are zero-padded to bring the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format for continuous mode operation is shown in Table 22 and
Table 24 in the Read/Write Data Formats section.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 26. A sample timing diagram
of a single-read SPI operation is shown in Figure 27. The COUT
pin goes from three-state to being driven at the beginning of
Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and the R/W bit and subsequent bytes carry the data.
Table 18. Generic Control Word Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 41
chip_adr[6:0], R/W 0000, subadr[11:8] subadr[7:0] data data
1 Continues to end of data.
CLATCH
CCLK
CDATA BYT
E 0 BYTE 1 BYTE 2 BYTE 3
06412-026
Figure 26. SPI Write to ADAU1701 Clocking (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 0 BYTE 1
HIGH-Z DATA DATA HIGH-Z
06412-027
BYTE 2
Figure 27. SPI Read from ADAU1701 Clocking (Single-Read Mode)
Data Sheet ADAU1701
Rev. C | Page 27 of 52
SELF-BOOT
On power-up, the ADAU1701 can load a program and a set
of parameters that have been saved in an external EEPROM.
Combined with the auxiliary ADC and the multipurpose pins,
this eliminates the need for a microcontroller in the system. The
self-booting is accomplished by the ADAU1701 acting as a master
on the I2C bus on startup, which occurs when the SELFBOOT
pin is set high. The ADAU1701 cannot self-boot in SPI mode.
The maximum necessary EEPROM size for program and
parameters is 9248 bytes, or just over 8.5 kB. This does not
include register settings or overhead bytes, but such factors do
not add a significant number of bytes. This much memory is
only needed if the program RAM (1024 × five bytes), parameter
RAM (1024 × four bytes), and interface registers (8 × four bytes)
are completely full. Most applications do not use the full program
and parameter RAMs, so an 8 kB EEPROM should be sufficient.
A self-boot operation is triggered on the rising edge of RESET
when the SELFBOOT and WP pins are set high. The
ADAU1701reads the program, parameters, and register settings
from the EEPROM. After the ADAU1701 finishes self-booting,
additional messages can be sent to the ADAU1701 on the I2C bus,
although this typically is not necessary in a self-booting
application. The I2C device address is 0x68 for a write and 0x69
for a read in this mode. The ADDRx pins have different
functions when the chip is in this mode, so the settings on them
can be ignored.
The ADAU1701 does not self-boot if WP is set low. Holding
this pin low allows the EEPROM to be programmed in-circuit.
The WP pin is pulled low (it typically has a resistor pull-up) to
enable writes to the EEPROM, but this in turn disables the self-
boot function until the WP pin is returned high.
The ADAU1701 is a master on the I2C bus during self-boot and
writeback. Although it is uncommon for an application using
self-boot to also have a microcontroller connected to the control
lines, care should be taken that no other device tries to write to the
I2C bus during self-boot or writeback. The ADAU1701 generates
SCL at 8 × fS; therefore, for a fS of 48 kHz, SCL runs at 384 kHz.
SCL has a duty cycle of 3/8 in accordance with the I2C specification.
The ADAU1701 reads from EEPROM Chip Address 0xA1. The
LSBs of the addresses of some EEPROMs are pin configurable;
in most cases, these pins should be tied low to set this address.
EEPROM Format
The EEPROM data contains a sequence of messages. Each
discrete message is one of the seven types defined in Table 19
and consists of a sequence of one or more bytes. The first byte
identifies the message type. Bytes are written MSB first. Most
messages are block write (0x01) types, which are used for writing
to the ADAU1701 program RAM, parameter RAM, and control
registers.
The body of the message following the message type should
start with a 0x00 byte; this is the chip address. As with all other
control port transactions, following the chip address is a 2-byte
register/memory address field.
Figure 28 shows an example of what should be stored in the
EEPROM, starting with EEPROM Address 0. In this example,
the interface registers are first set to control port write mode
(Line 1), which is followed by 18 no-operation (no-op) bytes
(Line 2 to Line 4) so that the interface register data appears on
Page 2 of the EEPROM. Next follows the write header (Line 4)
and then 32 bytes of interface register data (Line 5 to Line 8).
Finally, the program RAM data, starting at ADAU1701 Address
0x04 0x00 is written (Line 9 to Line 11). In this example, the
program length is 70 words, or 350 bytes, so 332 more bytes are
included in the EEPROM but are not shown in Figure 28.
Writeback
A writeback occurs when the WB pin is triggered and data is
written to the EEPROM from the ADAU1701. This function is
typically used to save the volume setting and other parameter
settings to the EEPROM just before power is removed from the
system. A rising edge on the WB pin triggers a writeback when
the device is in self-boot mode, unless a message to set the WB
to the falling edge sensitive (0x05) is contained in the self-boot
message sequence. Only one writeback takes place unless a
message to set multiple writebacks (0x04) is contained in the
self-boot message sequence. The WP pin is pulled low when a
writeback is triggered to allow writing to the EEPROM.
The ADAU1701 is only capable of writing back the contents of
the interface registers to the EEPROM. These registers are usually
set by the DSP program, but can also be written to directly after
setting Bit 6 of the core control register. The parameter settings
that should be saved are configured in SigmaStudio.
ADAU1701 Data Sheet
Rev. C | Page 28 of 52
The writeback function writes data from the ADAU1701
interface registers to the second page of the self-boot EEPROM,
Address 32 to Address 63. Starting at EEPROM Address 26
(so that the interface register data begins at Address 32), the
EEPROM should be programmed with six bytes—the message
byte (0x01), two length bytes, the chip address (0x00), and the
2-byte subaddress for the interface registers (0x08 0x00). There
must be a message to the DSP core control register to enable
writing to the interface registers prior to the interface register
data in the EEPROM. This should be stored in EEPROM
Address 0. No-op messages (0x03) can be used in between
messages to ensure that these conditions are met.
The ADAU1701 writes to EEPROM Chip Address 0xA0. The
LSBs of the addresses of some EEPROMs are pin configurable; in
most cases, these pins should be tied low to set the address to 0xA0.
The maximum number of bytes that is written back from the
ADAU1701 is 35 (eight 4-byte interface registers plus three
bytes of EEPROM-addressing overhead). With SCL running at
384 kHz, the writeback operation takes approximately 73 μs to
complete after being triggered. Ensure that sufficient power is
available to the system to allow enough time for a writeback to
complete, especially if the WB signal is triggered from a falling
power supply voltage.
Table 19. EEPROM Message Types
Message ID Message Type Following Bytes
0x00 End None
0x01 Write Two bytes indicating message length followed by appropriate
number of data bytes
0x02 Delay Two bytes for delay
0x03 No operation executed None
0x04 Set multiple writeback None
0x05 Set WB to falling edge sensitive None
0x06 End and wait for writeback None
0x01 0x00 0x05 0x00 0x08 0x1C 0x00 0x40
WRITE LENGTH DEVICE
ADDRESS
CORE CONTROL REGISTER
ADDRESS
CORE CONTROL REGISTER
DATA
0x01 0x001 0x61 0x00 0x04 0x00 0x00 0x00
WRITE LENGTH DEVICE
ADDRESS
PROGRAM RAM ADDRESS PROGRAM RAM DATA
0x00 0x00 0x01 0x00 0x00 0x00 0xE8 0x01
PROGRAM RAM DATA
0x00 0x00 0x00 0x00 0x01 0x00 0x08 0x00
PROGRAM RAM DATA (CONTINUES FOR 332 MORE BYTES)
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03
NO-OP BYTES
0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03
NO-OP BYTES
0x03 0x03 0x01 0x00 0x23 0x00 0x08 0x00
LENGTH DEVICE
ADDRESS
INTERFACE REGISTER
ADDRESS
WRITENO-OP BYTES
06412-039
Figure 28. EEPROM Data Example
Data Sheet ADAU1701
Rev. C | Page 29 of 52
SIGNAL PROCESSING
The ADAU1701 is designed to provide all audio signal processing
functions commonly used in stereo or multichannel playback
systems. The signal processing flow is designed using the
SigmaStudio software, which allows graphical entry and real-
time control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
NUMERIC FORMATS
DSP systems commonly use a standard numeric format.
Fractional number systems are specified by an A.B format,
where A is the number of bits to the left of the decimal point
and B is the number of bits to the right of the decimal point.
The ADAU1701 uses the same numeric format for both the
parameter and data values. The format is as follows.
Numerical Format: 5.23
Linear range: −16.0 to (+16.0 − 1 LSB)
Examples:
1000 0000 0000 0000 0000 0000 0000 = −16.0
1110 0000 0000 0000 0000 0000 0000 = −4.0
1111 1000 0000 0000 0000 0000 0000 = −1.0
1111 1110 0000 0000 0000 0000 0000 = −0.25
1111 1111 0011 0011 0011 0011 0011 = −0.1
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)
0000 0000 0000 0000 0000 0000 0000 = 0.0
0000 0000 1100 1100 1100 1100 1101 = 0.1
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB).
The serial port accepts up to 24 bits on the input and is sign-
extended to the full 28 bits of the DSP core. This allows internal
gains of up to 24 dB without internal clipping.
A digital clipper circuit is used between the output of the DSP
core and the DACs or serial port outputs (see Figure 29). This
clips the top four bits of the signal to produce a 24-bit output
with a range of 1.0 (minus 1 LSB) to −1.0. Figure 29 shows the
maximum signal levels at each point in the data flow in both
binary and decibel levels.
4-BIT SIGN EXTENSION
DATA IN 1.23
(0dB) 1.23
(0dB) 1.23
(0dB)
5.23
(24dB) 5.23
(24dB)
SERIAL
PORT
SIGNAL
PROCESSING
(5.23 FORMAT)
DIGITAL
CLIPPER
06412-028
Figure 29. Numeric Precision and Clipping Structure
PROGRAMMING
On power-up, the ADAU1701default program passes the
unprocessed input signals to the outputs (shown in Figure 13),
but the outputs are muted by default (see the Power-Up Sequence
section). There are 1024 instruction cycles per audio sample,
resulting in about 50 MIPS available. The SigmaDSP runs in a
stream-oriented manner, meaning that all 1024 instructions are
executed each sample period. The ADAU1701 can also be set up to
accept double- or quad-speed inputs by reducing the number of
instructions per sample that are set in the core control register.
The part can be easily programmed using SigmaStudio (Figure 30),
a graphical tool provided by Analog Devices. No knowledge of
writing line-level DSP code is required. More information about
SigmaStudio can be found at www.analog.com.
06412-029
Figure 30. SigmaStudio Screen Shot
Table 20. RAM Map and Read/Write Modes
ADAU1701 Data Sheet
Rev. C | Page 30 of 52
RAMS AND REGISTERS
Table 20. RAM Map and Read/Write Modes
Memory Size Address Range Read Write Write Modes
Parameter RAM 1024 × 32 0 to 1023 (0x0000 to 0x03FF) Yes Yes Direct write1 safeload write
Program RAM
1024 × 40
1024 to 2047 (0x0400 to 0x07FF)
Yes
Yes
Direct write
1
1 Internal registers should be cleared first to avoid clicks/pops.
ADDRESS MAPS
Table 20 shows the RAM map and Table 31 shows the ADAU1701
register map. The address space encompasses a set of registers
and two RAMs: one holds signal processing parameters and one
holds the program instructions. The program RAM and parameter
RAM are initialized on power-up from on-board boot ROMs
(see the Power-Up Sequence section).
All RAMs and registers have a default value of all 0s, except for
the program RAM, which is loaded with the default program
(see the Initialization section).
PARAMETER RAM
The parameter RAM is 32 bits wide and occupies Address 0
to Address 1023. Each parameter is padded with four 0s before
the MSB to extend the 28-bit word to a full 4-byte width. The
parameter RAM is initialized to all 0s on power-up. The data
format of the parameter RAM is twos complement, 5.23.
This means that the coefficients can range from +16.0 (minus
1 LSB) to −16.0, with 1.0 represented by the binary word
0000 1000 0000 0000 0000 0000 0000 or by the hexadecimal
word 0x00 0x80 0x00 0x00.
The parameter RAM can be written using one of the two
following methods: a direct read/write or a safeload write.
Direct Read/Write
The direct read/write method allows direct access to the program
RAM and parameter RAM. This mode of operation is typically
used when loading a new RAM using burst mode addressing. The
clear registers bit in the core control register should be set to 0
using this mode to avoid any clicks or pops in the outputs. Note
that this mode can be used during live program execution, but
because there is no handshaking between the core and the control
port, the parameter RAM is unavailable to the DSP core during
control writes, resulting in clicks and pops in the audio stream.
Safeload Write
Up to five safeload registers can be loaded with the parameter
RAM address/data. The data is then transferred to the requested
address when the RAM is not busy. This method can be used
for dynamic updates while live program material is playing
through the ADAU1701. For example, a complete update of one
biquad section can occur in one audio frame while the RAM is
not busy. This method is not available for writing to the
program RAM or control registers.
DATA RAM
The ADAU1701 data RAM is used to store audio data words for
processing. For the most part, this process is transparent to the
user. The user cannot address this RAM space, which has a size
of 2k words, directly from the control port.
Data RAM utilization should be considered when implementing
blocks that require large amounts of data RAM space, such as
delays. The SigmaDSP core processes delay times in one-sample
increments; therefore, the total pool of delay available to the user
equals 2048 multiplied by the sample period. For a fS of 48 kHz,
the pool of available delay is a maximum of about 43 ms. In
practice, this much data memory is not available to the user
because every block in a design uses a few data memory locations
for its processing. In most DSP programs, this does not signifi-
cantly impact the total delay time. The SigmaStudio compiler
manages the data RAM and indicates if the number of addresses
needed in the design exceeds the maximum available.
READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to
be byte oriented. This allows easy programming of common
microcontroller chips. To fit into a byte-oriented format, 0s are
appended to the data fields before the MSB to extend the data-
word to eight bits. For example, 28-bit words written to the
parameter RAM are appended with four leading 0s to equal
32 bits (four bytes); 40-bit words written to the program RAM
are not appended with 0s because they are already a full five bytes.
These zero-padded data fields are appended to a 3-byte field
consisting of a 7-bit chip address, a read/write bit, and an 11-bit
RAM/register address. The control port knows how many data
bytes to expect based on the address given in the first three bytes.
The total number of bytes for a single-location write command
can vary from four bytes (for a control register write) to eight
bytes (for a program RAM write). Burst mode can be used to fill
contiguous register or RAM locations. A burst mode write begins
by writing the address and data of the first RAM or register location
to be written. Rather than ending the control port transaction
(by issuing a stop command in I2C mode or by bringing the
CLATCH signal high in SPI mode after the data-word), as
would be done in a single-address write, the next data-word
can be immediately written without specifying its address. The
ADAU1701 control port auto-increments the address of each write
even across the boundaries of the different RAMs and registers.
Table 22 and Table 24 show examples of burst mode writes.
Table 21. Parameter RAM Read/Write Format (Single Address) W Table 22. Parameter RAM Block Read/Write Format (Burst Mode) cmpjddemW Table 23. Program RAM Read/Write Format (Single Address) W Table 24. Program RAM Block Read/Write Format (Burst Mode) W Table 25. Control Register Read/Write Format (Core, Serial 0m 0, Serial Out 1) W W Table 27. Data Capture Register Write Format W Table 28. Data Capture (Control Port Readback) Register Read Format W Table 29. Safeload Address Register Write Format W Table 30. Safeload Data Register Write Format W
Data Sheet ADAU1701
Rev. C | Page 31 of 52
Table 21. Parameter RAM Read/Write Format (Single Address)
Byte 0 Byte 1 Byte 2 Byte 3 Bytes[4:6]
chip_adr[6:0], W/R 000000, param_adr[9:8] param_adr[7:0] 0000, param[27:24] param[23:0]
Table 22. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0 Byte 1 Byte 2 Byte 3 Bytes[4:6] Bytes[7:10] Bytes[11:14]
chip_adr[6:0], W/R 000000, param_adr[9:8] param_adr[7:0] 0000, param[27:24] param[23:0]
<—param_adr> param_adr + 1 param_adr + 2
Table 23. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
chip_adr[6:0], W/R 00000, prog_adr[10:8] prog_adr[7:0] prog[39:0]
Table 24. Program RAM Block Read/Write Format (Burst Mode)
Byte 0 Byte 1 Byte 2 Bytes[3:7] Bytes[8:12] Bytes[13:17]
chip_adr[6:0],
W
/R
00000, prog_adr[10:8]
prog_adr[7:0]
prog[39:0]
<—prog_adr—> prog_adr + 1 prog_adr + 2
Table 25. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1)
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
chip_adr[6:0], W/R 0000, reg_adr[11:8] reg_adr[7:0] data[15:8] data[7:0]
Table 26. Control Register Read/Write Format (RAM Configuration, Serial Input)
Byte 0 Byte 1 Byte 2 Byte 3
chip_adr[6:0], W/R 0000, reg_adr[11:8] reg_adr[7:0] data[7:0]
Table 27. Data Capture Register Write Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
chip_adr[6:0], W/R 0000, data_capture_adr[11:8] data_capture_adr[7:0] 000, progCount[10:6]1 progCount[5:0]1, regSel[1:0]2
1 progCount[10:0] is the value of the program counter when the data capture occurs (the table of values is generated by the SigmaStudio compiler).
2 regSel[1:0] selects one of four registers (see the 2074 to 2075 (0X081A to 0X081B)Data Capture Registers section).
Table 28. Data Capture (Control Port Readback) Register Read Format
Byte 0 Byte 1 Byte 2 Bytes[3:5]
chip_adr[6:0], W/R 0000, data_capture_adr[11:8] data_capture_adr[7:0] data[23:0]
Table 29. Safeload Address Register Write Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
chip_adr[6:0],
W
/R
0000, safeload_adr[11:8]
safeload_adr[7:0]
000000, param_adr[9:8]
param_adr[7:0]
Table 30. Safeload Data Register Write Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Bytes[5:7]
chip_adr[6:0], W/R 0000, safeload_adr[11:8] safeload_adr[7:0] 00000000 0000, data[27:24] data[23:0]
ADAU1701 Data Sheet
Rev. C | Page 32 of 52
CONTROL REGISTER MAP
Table 31. Register Map1
MSB LSB
Register No. D39 D38 D37 D36 D35 D34 D33 D32
Address of D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Hex Dec Bytes Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x0800 2048 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0801 2049 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0802 2050 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0803 2051 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0804 2052 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0805 2053 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0806 2054 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0807 2055 4 Interface 0[31:16] 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
Interface 0[15:0] IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
0x0808 2056 2 GPIO pin setting 0 0 0 0 MP11 MP10 MP09 MP08 MP07 MP06 MP05 MP04 MP03 MP02 MP01 MP00 0x0000
0x0809 2057 2 Auxiliary ADC Data 0 0 0 0 0 AA11 AA10 AA09 AA08 AA07 AA06 AA05 AA04 AA03 AA02 AA01 AA00 0x0000
0x080A 2058 2 Auxiliary ADC Data 1 0 0 0 0 AA11 AA10 AA09 AA08 AA07 AA06 AA05 AA04 AA03 AA02 AA01 AA00 0x0000
0x080B 2059 2 Auxiliary ADC Data 2 0 0 0 0 AA11 AA10 AA09 AA08 AA07 AA06 AA05 AA04 AA03 AA02 AA01 AA00 0x0000
0x080C 2060 2 Auxiliary ADC Data 3 0 0 0 0 AA11 AA10 AA09 AA08 AA07 AA06 AA05 AA04 AA03 AA02 AA01 AA00 0x0000
0x080D 2061 5 Reserved[39:32] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x00
Reserved[31:16] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
Reserved[15:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
0x080E 2062 5 Reserved[39:32] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x00
Reserved[31:16] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
Reserved[15:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
0x080F 2063 5 Reserved[39:32] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x00
Reserved[31:16] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
Reserved[15:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
0x0810 2064 5 Safeload Data 0[39:32] SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00
Safeload Data 0[31:16] SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000
Safeload Data 0[15:0] SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
0x0811 2065 5 Safeload Data 1[39:32] SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00
Safeload Data 1[31:16] SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000
Safeload Data 1[15:0] SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
0x0812 2066 5 Safeload Data 2[39:32] SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00
Safeload Data 2[31:16] SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000
Safeload Data 2[15:0] SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
0x0813 2067 5 Safeload Data 3[39:32] SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00
Safeload Data 3[31:16] SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000
Safeload Data 3[15:0] SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
0x0814 2068 5 Safeload Data 4[39:32] SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00
Safeload Data 4[31:16] SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000
Safeload Data 4[15:0] SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
0x0815 2069 2 Safeload Address 0 0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
0x0816 2070 2 Safeload Address 1 0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
0x0817 2071 2 Safeload Address 2 0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
0x0818 2072 2 Safeload Address 3 0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
0x0819 2073 2 Safeload Address 4 0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
0x081A 2074 2 Data Capture 0 0 0 0 0 PC09 PC08 PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 RS01 RS00 0x0000
0x081B 2075 2 Data Capture 1 0 0 0 0 PC09 PC08 PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 RS01 RS00 0x0000
0x081C 2076 2 DSP core control RSVD RSVD GD1 GD0 RSVD RSVD RSVD AACW GPCW IFCW IST ADM DAM CR SR1 SR0 0x0000
0x081D 2077 1 Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x00
0x081E 2078 2 Serial output control 0 0 OLRP OBP M/S OBF1 OBF0 OLF1 OLF0 FST TDM MSB2 MSB1 MSB0 OWL1 OWL0 0x0000
0x081F 2079 1 Serial input control 0 0 0 ILP IBP M2 M1 M0 0x00
Data Sheet ADAU1701
Rev. C | Page 33 of 52
MSB LSB
Register No. D39 D38 D37 D36 D35 D34 D33 D32
Address of D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Hex Dec Bytes Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x0820 2080 3 MP Pin Config. 0[23:16] MP53 MP52 MP51 MP50 MP43 MP42 MP41 MP40 0x00
MP Pin Config. 0[15:0] MP33 MP32 MP31 MP30 MP23 MP22 MP21 MP20 MP13 MP12 MP11 MP10 MP03 MP02 MP01 MP00 0x0000
0x0821 2081 3 MP Pin Config. 1[23:16] MP113 MP112 MP111 MP110 MP103 MP102 MP101 MP100 0x00
MP Pin Config. 1[15:0] MP93 MP92 MP91 MP90 MP83 MP82 MP81 MP80 MP73 MP72 MP71 MP70 MP63 MP62 MP61 MP60 0x0000
0x0822 2082 2 Auxiliary ADC and power RSVD RSVD RSVD RSVD RSVD RSVD FIL1 FIL0 AAPD VBPD VRPD RSVD D0PD D1PD D2PD D3PD 0x0000
control
0x0823 2083 2 Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
0x0824 2084 2 Auxiliary ADC enable AAEN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
0x0825 2085 2 Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000
0x0826 2086 2 Oscillator power-down RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPD RSVD RSVD 0x0000
0x0827 2087 2 DAC setup RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DS1 DS0 0x0000
1 Shading indicates that registers do not fill these locations, so control bits do not exist in these locations.
ADAU1701 Data Sheet
Rev. C | Page 34 of 52
CONTROL REGISTER DETAILS
2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE
REGISTERS
The interface registers are used in self-boot mode to save
parameters that need to be written to the external EEPROM.
The ADAU1701 then recalls these parameters from the
EEPROM after the next reset or power-up. Therefore, system
parameters such as volume and EQ settings can be saved during
power-down and recalled the next time the system is turned on.
There are eight 32-bit interface registers, which allow eight 28-bit
(plus zero-padding) parameters to be saved. The parameters to
be saved in these registers are selected in the graphical
programming tools. These registers are updated with their
corresponding parameter RAM data once per sample period.
An edge, which can be set to be either rising or falling, triggers
the ADAU1701 to write the current contents of the interface
registers to the EEPROM. See the Self-Boot section for details.
The user can write directly to the interface registers after the
interface registers control port write mode (IFCW) in the DSP core
control register has been set. In this mode, the data in the registers
is written from the control port, not from the DSP core.
Table 32. Interface Register Bit Map
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000
IF15 IF14 IF13 IF12 IF11 IF10 IF09 IF08 IF07 IF06 IF05 IF04 IF03 IF02 IF01 IF00 0x0000
Table 33.
Bit Name Description
IF[27:0] Interface register 28-bit parameter
Table 34. GPlO Pin Selling Regism Bi: Map Table 35.
Data Sheet ADAU1701
Rev. C | Page 35 of 52
2056 (0x0808)GPIO PIN SETTING REGISTER
This register allows the user to set the GPIO pins through the
control port. High or low settings can be directly written to or
read from this register after setting the GPIO pin setting register
control port write mode (GPCW) in the core control register.
This register is updated once every LRCLK frame (1/fS).
Table 34. GPIO Pin Setting Register Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0 0 0 0 MP11 MP10 MP09 MP08 MP07 MP06 MP05 MP04 MP03 MP02 MP01 MP00 0x0000
Table 35.
Bit Name Description
MP[11:0] Setting of multipurpose pin when controlled through SPI or I2C
Table 36. Auxiliary ADC Data Register Bil Map
ADAU1701 Data Sheet
Rev. C | Page 36 of 52
2057 TO 2060 (0x0809 TO 0x080C)AUXILIARY
ADC DATA REGISTERS
These registers hold the data generated by the 4-channel
auxiliary ADC. The ADCs have eight bits of precision and can
be extended to 12 bits if filtering is selected via Bits FIL[1:0] of
the auxiliary ADC and power control register. The SigmaDSP
program reads this data as a 1.11 format data-word with a range
of 0 to 1.0. This data-word is mapped to the 5.23 format
parameter word with the four MSBs and 12 LSBs set to 0. A
full-scale code of 255 results in a value of 1.0. These registers
can be written to directly if the auxiliary ADC data registers
control port write mode (AACW) bit is set in the DSP core
control register.
Table 36. Auxiliary ADC Data Register Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0 0 0 0 AA11 AA10 AA09 AA08 AA07 AA06 AA05 AA04 AA03 AA02 AA01 AA00 0x0000
Table 37.
Bit Name Description
AA[11:0] Auxiliary ADC output data, MSB first
Data Sheet ADAU1701
Rev. C | Page 37 of 52
2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD
DATA REGISTERS
Many applications require real-time microcontroller control of
signal processing parameters, such as filter coefficients, mixer
gains, multichannel virtualizing parameters, or dynamics
processing curves. When controlling a biquad filter, for
example, all of the parameters must be updated at the same
time. Doing so prevents the filter from executing with a mix of
old and new coefficients for one or two audio frames, thus
avoiding temporary instability and transients that may take a
long time to decay. To accomplish this, the ADAU1701 uses
safeload data registers to simultaneously load a set of five 28-bit
values to the desired parameter RAM address. Five registers are
used because a biquad filter uses five coefficients and, as
previously mentioned, it is desirable to do a complete update in
one transaction.
The first step in performing a safeload operation is writing the
parameter address to one of the safeload address registers (2069
to 2073). The 10-bit data-word to be written is the address in
parameter RAM to which the safeload is being performed. After
this address is written, the 28-bit data-word can be written to
the corresponding safeload data register (2064 to 2068).
The data formats for these writes are detailed in Table 29 and
Table 30. Table 38 shows how each of the five address registers
maps to its corresponding data register.
After the address and data registers are loaded, set the initiate
safeload transfer bit in the core control register to initiate the
loading into RAM. Each of the five safeload registers takes one of
the 1024 core instructions to load into the parameter RAM. The
total program lengths should, therefore, be limited to 1019 cycles
(1024 minus 5) to ensure that the SigmaDSP core always has at
least five cycles available. The safeload is guaranteed to occur
within one LRCLK period (21 μs for a fS of 48 kHz) of the initiate
safeload transfer bit being set.
The safeload logic automatically sends data to be loaded into
RAM from only those safeload registers that have been written
to since the last safeload operation. For example, if two parameters
are to be updated in the RAM, only two of the five safeload registers
must be written. When the initiate safeload transfer bit is asserted,
only data from those two registers are sent to the RAM; the other
three registers are not sent to the RAM and may hold old or
invalid data.
Table 38. Safeload Address and Data Register Mapping
Safeload
Register
Safeload
Address Register
Safeload
Data Register
0 2069 2064
1 2070 2065
2 2071 2066
3 2072 2067
4 2073 2068
Table 39. Safeload Registers Bit Map
D39 D38 D37 D36 D35 D34 D33 D32
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00
SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000
SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
Table 40.
Bit Name Description
SD[39:0] Safeload Data. Data (program, parameters, register contents) to be loaded into the RAMs or
registers.
2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
Table 41. Safeload Address Registers Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
Table 42.
Bit Name Description
SA[11:0] Safeload Address. Address of data that is to be loaded into the RAMs or registers
Table 44.
ADAU1701 Data Sheet
Rev. C | Page 38 of 52
2074 TO 2075 (0x081A TO 0x081B)DATA
CAPTURE REGISTERS
The ADAU1701 data capture feature allows the data at any node
in the signal processing flow to be sent to one of two readable
registers. This feature is useful for monitoring and displaying
information about internal signal levels or compressor/limiter
activity.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number
between 0 and 1023 that corresponds to the program step
number where the capture is to occur. The register select field
programs one of four registers in the DSP core that transfers
this information to the data capture register when the program
counter reaches this step.
The captured data is in 5.19, twos complement data format,
which comes from the internal 5.23 data-word with the four
LSBs truncated.
The data that must be written to set up the data capture is a
concatenation of the 10-bit program count index with the 2-bit
register select field. The capture count and register select values
that correspond to the desired point to be monitored in the
signal processing flow can be found in a file output from the
program compiler. The capture registers can be accessed by
reading from Location 2074 and Location 2075. The format for
writing and reading to the data capture registers is shown in
Table 27 and Table 28.
Table 43. Safeload Data Registers Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0 0 0 0 PC09 PC08 PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 RS01 RS00 0x0000
Table 44.
Bit Name Description
PC[9:0] 10-bit program counter address
RS[1:0] Select the register to be transferred to the data capture output
RS[1:0] Register
00 Multiplier X input (Mult_X_input)
01 Multiplier Y input (Mult_Y_input)
10 Multiplier-accumulator output (MAC_out)
11 Accumulator feedback (Accum_fback)
Data Sheet ADAU1701
Rev. C | Page 39 of 52
2076 (0x081C)DSP CORE CONTROL REGISTER
Table 45. DSP Core Control Register Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
RSVD
RSVD
GD1
GD0
RSVD
RSVD
RSVD
AACW
GPCW
IFCW
IST
ADM
DAM
CR
SR1
SR0
0x0000
Table 46. DSP Core Control Register
Bit Name Description
GD[1:0] GPIO Debounce Control. Sets debounce time of multipurpose pins that are set as GPIO inputs.
GD[1:0] Time (ms)
00 20
01 40
10
10
11 5
AACW Auxiliary ADC Data Registers Control Port Write Mode. Setting this bit allows data to be written directly to the
auxiliary ADC data registers (2057 to 2060) from the control port. When this bit is set, the auxiliary ADC data
registers ignore the settings on the multipurpose pins.
GPCW GPIO Pin Setting Register Control Port Write Mode. When this bit is set, the GPIO pin setting register (2056) can
be written to directly from the control port and this register ignores the input settings on the multipurpose
pins.
IFCW Interface Registers Control Port Write Mode. When this bit is set, data can be written directly to the interface
registers (2048 to 2055) from the control port. In that state, the interface registers are not written from the
SigmaDSP program.
IST Initiate Safeload Transfer. Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is
automatically cleared when the operation is complete. There are five safeload register pairs (address/data);
only those registers that have been written since the last safeload event are transferred to the parameter RAM.
ADM Mute ADCs. This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the ADCs.
DAM Mute DACs. This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the DACs.
CR Clear Internal Registers to 0. This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass
through the SigmaDSP core.
SR[1:0] Sample Rate. These bits set the number of DSP instructions for every sample and the sample rate at which the
ADAU1701 operates. At the default setting of 1×, there are 1024 instructions per audio sample. This setting
should be used with sample rates such as 48 kHz and 44.1 kHz.
At the 2
× setting, the number of instructions per frame is halved to 512 and the ADCs and DACs nominally run
at a 96 kHz sample rate.
At the 4× setting, there are 256 instructions per cycle and the converters run at a 192 kHz sample rate.
SR[1:0] Setting
00 (1024 instructions)
01 (512 instructions)
10 (256 instructions)
11
Reserved
ADAU1701 Data Sheet
Rev. C | Page 40 of 52
2078 (0x081E)SERIAL OUTPUT CONTROL REGISTER
Table 47. Serial Output Control Register Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0
0
OLRP
OBP
M/S
OBF1
OBF0
OLF1
OLF0
FST
TDM
MSB2
MSB1
MSB0
OWL1
OWL0
0x0000
Table 48.
Bit Name Description
OLRP OUTPUT_LRCLK Polarity. When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK is
low and the right-channel data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right-
channel data is clocked when OUTPUT_LRCLK is low and the left-channel data is clocked when
OUTPUT_LRCLK is high.
OBP OUTPUT_BCLK Polarity. This bit controls on which edge of the bit clock the output data is clocked. Data
changes on the falling edge of OUTPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is
set to 1.
M/S Master/Slave. This bit sets whether the output port is a clock master or slave. The default setting is slave; on
power-up, the OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time
they become clock outputs.
OBF[1:0] OUTPUT_BCLK Frequency (Master Mode Only). When the output port is being used as a clock master, these
bits set the frequency of the output bit clock, which is divided down from an internal 1024 × fS clock
(49.152 MHz for a fS of 48 kHz).
OBF[1:0] Setting
00 Internal clock/16
01
Internal clock/8
10 Internal clock/4
11 Internal clock/2
OLF[1:0]
OUTPUT_LRCLK Frequency (Master Mode Only). When the output port is used as a clock master, these bits set
the frequency of the output word clock on the OUTPUT_LRCLK pins, which is divided down from an internal
1024 × fS clock (49.152 MHz for a fS of 48 kHz).
OLF[1:0]
Setting
00 Internal clock/1024
01 Internal clock/512
10 Internal clock/256
11 Reserved
FST Frame Sync Type. This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the
signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of
one bit clock at the beginning of the data frame.
TDM TDM Enable. Setting this bit to 1 changes the output port from four serial stereo outputs to a single
8-channel TDM output stream on the SDATA_OUT0 pin (MP6).
MSB[2:0] MSB Position. These three bits set the position of the MSB of data with respect to the LRCLK edge. The data
output of theADAU1701 is always MSB first.
MSB[2:0] Setting
000 Delay by 1
001 Delay by 0
010 Delay by 8
011 Delay by 12
100 Delay by 16
101 Reserved
111 Reserved
OWL[1:0] Output Word Length. These bits set the word length of the output data-word. All bits following the LSB are
set to 0.
OWL[1:0] Setting
00 24 bits
01 20 bits
10 16 bits
11 Reserved
Data Sheet ADAU1701
Rev. C | Page 41 of 52
2079 (0x081F)SERIAL INPUT CONTROL REGISTER
Table 49. Serial Input Control Register Bit Map
D7 D6 D5 D4 D3 D2 D1 D0 Default
0
0
0
ILP
IBP
M2
M1
M0
0x00
Table 50.
Bit Name Description
ILP INPUT_LRCLK Polarity. When this bit is set to 0, the left-channel data on the SDATA_INx pins is clocked when
INPUT_LRCLK is low and the right-channel data is clocked when INPUT_LRCLK is high. When this bit is set to 1,
the clocking of these channels is
reversed. In TDM mode when this bit is set to 0, data is clocked in, starting with
the next appropriate BCLK edge (set in Bit 3 of this register) after a falling edge on the INPUT_LRCLK pin. When
this bit is set to 1 and the device is running in TDM mode, the input data is valid on the BCLK edge after a rising
edge on the word clock (INPUT_LRCLK). INPUT_LRCLK can also operate with a pulse input, rather than a clock.
In this case, the first edge of the pulse is used by the ADAU1701 to start the data frame. When this polarity bit is
set to 0, a low pulse should be used; when the bit it set to 1, a high pulse should be used.
IBP INPUT_BCLK Polarity. This bit controls on which edge of the bit clock the input data changes and on which edge
it is clocked. Data changes on the falling edge of INPUT_BCLK when this bit is set to 0 and on the rising edge when
this bit is set at 1.
M[2:0] Serial Input Mode. These two bits control the data format that the input port expects to receive. Bit 3 and Bit 4
of this control register override the settings of Bits[2:0]; therefore, all four bits must be changed together for
proper operation in some modes. The clock diagrams for these modes are shown in Figure 32, Figure 33, and
Figure 34. Note that for left-justified and right-justified modes, the LRCLK polarity is high and then low, which is
the opposite of the default setting for I L P.