Hoja de datos de PL 3120® and PL 3150® de Echelon Corporation

5 ECHELDI'I
®
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PL 3120®and PL 3150®Power
Line Smart Transceivers
Feature
Combines an ANSI-709.2 compliant Power Line Transceiver with an ANSI 709.1
compliant Neuron® 3120 or Neuron 3150 processor core
Designed to comply with FCC, Industry Canada, Japan MPT, and European
CENELEC EN 50065-1 power line communications regulations
Supports CENELEC A-band and C-band operation
Dual carrier frequency mode and digital signal processing
4K Bytes of embedded EEPROM for application code and configuration data on
the PL 3120 Power Line Smart Transceiver and 0.5K Bytes of embedded EEP-
ROM for configuration data on the PL 3150 Power Line Smart Transceiver
Interface for external memory for applications with larger memory requirements
(PL 3150 Power Line Smart Transceiver only)
2K Bytes of embedded RAM for buffering network data and network variables
Full duplex hardware UART and SPI serial interfaces
12 I/O pins with 38 programmable standard I/O modes to minimize external
interface circuitry
-40 to +85°C operating temperature range
Overview
The PL 3120 and PL 3150 Power Line Smart Transceivers integrate a Neuron processor core
with a power line transceiver, making them ideal for appliance, audio/video, lighting, heat-
ing/cooling, security, metering, and irrigation applications. Essentially a system-on-a-chip, the
Power Line Smart Transceivers feature a highly reliable narrow-band power line transceiver,
an 8-bit Neuron processor core for running applications and managing network communica-
tions, a choice of on-board or external memory, and an extremely small form factor – all at a
price that is compelling for even the most cost-sensitive consumer product applications.
A Global Product
Compliant with FCC, Industry Canada, Japan MPT, and European CENELEC EN50065-1
regulations, the PL 3120 and PL 3150 Power Line Smart Transceivers can be used in applica-
tions worldwide.
The Power Line Smart Transceivers implement the CENELEC access protocol, which can be
enabled or disabled by the user. This eliminates the need for users to develop the complex
timing and access algorithms mandated under CENELEC EN50065-1. Additionally, the Power
E ECHELDI'I
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Line Smart Transceivers can operate in ei-
ther the CENELEC utility (A-band) or gen-
eral signaling (C-band) bands, eliminating
the need to stock multiple parts for
different applications.
Unmatched Performance
Intermittent noise sources, impedance
changes, and attenuation make the power
line a hostile signaling environment. The PL
3120 and PL 3150 Power Line Smart Trans-
ceivers incorporate a variety of technical
innovations to insure reliable operation:
Unique dual carrier frequency
feature automatically selects an al-
ternate secondary communication
frequency should the primary
frequency be blocked by noise;
Highly efficient, patented, low-over-
head forward error correction
(FEC) algorithm to overcome
errors induced by noise;
Sophisticated digital signal process-
ing, noise cancellation, and distor-
tion correction algorithms. These
features correct for a wide variety
of signaling impediments, including
impulsive noise, continuous tone
noise, and phase distortion;
High output, low distortion external
amplifier design that can deliver
1Ap-p into low impedance loads,
eliminating the need for expensive
phase couplers in typical residential
applications.
The combination of these special features
enable the Power Line Smart Transceivers
to operate reliably in the presence of con-
sumer electronics, power line intercoms,
motor noise, electronic ballasts, dimmers,
and other typical sources of interference.
The Power Line Smart Transceivers can
communicate over virtually any AC or
DC power mains, as well as unpowered
twisted pair, by way of a low-cost,
external coupling circuit.
The PL 3120 Power Line Smart Transceiver
is targeted at very low cost designs that
require up to 4K Bytes of application code,
and an ultra-compact 38 TSSOP package.
The chip includes 4K Bytes of EEPROM and
2K Bytes of RAM. The Neuron system
firmware and software application libraries
are contained in on-chip ROM.
The PL 3150 Power Line Smart Transceiver
is intended for applications that need to
address up to 58K Bytes of external mem-
ory (16K Bytes is dedicated to the Neuron
system firmware) using a 64 LQFP pack-
age. The chip includes 0.5K Bytes of
EEPROM and 2K Bytes of RAM.
The PL 3120 and PL 3150 Power Line Smart
Transceivers operate at either 6.5536MHz
or 10.0MHz. The 6.5536MHz clock fre-
quency enables the Power Line Smart
Transceiver to communicate in the CEN-
ELEC A-band, which is used for metering
and utility applications. The 10MHz clock
frequency supports the CENELEC C-band,
which is used for general purpose signaling
and all non-utility related applications.
Application programs stored in the embed-
ded EEPROM (PL 3120 Power Line Smart
Transceiver) or in the external non-volatile
memory (PL 3150 Power Line Smart Trans-
ceiver) may be updated over the power
line network. This valuable feature enables
products to be updated without physically
accessing them, i.e., from a local PC with a
power line interface or from a remote
service center through an i.LON® Internet
Server. The embedded EEPROM may be
written up to 10,000 times with no data
loss. Data stored in the EEPROM will be
retained for at least ten years.
Inexpensive Power Supply
The PL 3120 and PL3150 Power Line Smart
Transceivers use +8.5 to +18VDC and
+5VDC power supplies and support very
low receive mode current consumption.
The wide power supply range and very
low receive power requirements allow
the use of inexpensive power supplies.
Additionally, the Power Line Smart Trans-
ceivers incorporate a power management
feature that constantly monitors the status
of the device’s power supply. If during
transmission the power supply voltage
falls to a level that is insufficient to ensure
reliable signaling, the transceiver stops
transmitting until the power supply voltage
rises to an acceptable level. This unique
feature allows the use of a power supply
with one-third the current capacity other-
wise required. The net result is a reduction
in the size, cost, and thermal dissipation
of the power supply. Power management is
especially useful for high volume, low-cost
consumer products such as electrical
switches, motion detectors, outlets, light
sensors, and dim
Flexible I/O, Simple
Configuration
The PL 3120 and PL 3150 Power Line Smart
Transceivers provide 12 I/O pins which can
be configured to operate in one or more
of 38 predefined standard input/output
modes. Combining a wide range of I/O
models with two on-board timer/counters
enables the PL 3120 and PL 3150 Power
Line Smart Transceivers to interface with
application circuits using minimal external
logic or software development. The Power
Line Smart Transceivers also feature a full
duplex hardware UART supporting baud
rates of up to 115kbps, and an SPI interface
that operates up to 625kbps.
External Components
Only a small number of inexpensive exter-
nal components are required to create a
complete Power Line Smart Transceiver-
based device (see the PL 3120 / PL 3150
Power Line Smart Transceiver Block Dia-
gram). These components include:
Discrete interface circuitry com-
prised of roughly fifty components,
primarily resistors and capacitors.
This circuitry provides “front-end”
filtering for the on-chip A/D, and
implements the power amplifier
that drives the on-chip D/A transmit
signal onto the power line. Echelon
offers a comprehensive Power Line
Development Support Kit* (DSK)
with which customers can imple-
ment this interface circuitry. Contact
your salesperson for details about
purchasing a PL DSK.
Coupling circuit consisting of
approximately ten components,
mainly capacitors and inductors,
which acts as a simple high-pass
filter located between the Power
Line Smart Transceiver and the
power mains. This circuitry provides
surge and line transient protection
in addition to blocking the low fre-
quency, 50Hz/60Hz AC mains
signal. Detailed schematics are
provided in the PL 3120 / PL 3150
Power Line Smart Transceiver
Data Book.
The new RoHS compliant Revision
B Power Line Smart Transceivers
eliminate the need for an external
inverter, thereby reducing the cost
of external components. Circuits
without an external inverter can
only be used with Revision B parts
(15311R-1000 PL 3120 Power Line
Smart Transceiver and 15321R-960
PL 3150 Power Line Smart
Transceiver).
*Echelon Corporation has developed and
patented certain methods of implementing
circuitry external to the PL 3120 and PL 3150
Power Line Smart Transceiver chips. These
patents are licensed pursuant to the Echelon
Power Line Smart Transceiver Development
Support Kit License Agreement.
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PL 3120 / PL 3150 Power Line Smart Transceiver Block Diagram
NOTE:
1The schematic, bill of materials, and layout plots for the Discrete Interface Circuitry
are provided in the PL DSK Power Line Smart Transceiver Development Support Kit.
General Specifications
Function Description
Emissions compliance Designed to be compliant with FCC, Industry Canada, Japan MPT, and CENELEC EN50065-1
specification for low-voltage signaling
Bit rate 5.4kbps raw bit rate in CENELEC C-band and 3.6kbps in CENELEC A-band
Communication technique Dual Frequency BPSK with DSP-enhanced receiver
Carrier frequencies 132kHz (primary) and 115kHz (secondary) in CENELEC C-band and
86kHz (primary) and 75kHz (secondary) in CENELEC A-band
RoHS Compliance Models 15311R-1000 and 15321R-960 are designed to be compliant with European Directive
2002/95/EC on Restriction of Hazardous Substances (RoHS) in electrical and electronic
equipment.
PL 3120 Power Line Smart Transceiver Pinout Diagram
38 Pin TSSOP
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PL 3120 and PL 3150 Power Line Smart Transceiver Pin Descriptions
Pin Name Type Pin Functions PL 3120-E4T10 PL 3150-L10
38 TSSOP Pin No. 64 LQFP Pin No.
XIN Input Oscillator connection or external clock input. 29 34
XOUT Output Oscillator connection. 30 35
RESET Digital I/O (Built-in Pull-up) Reset pin (active LOW). 35 49
Note: The maximum external capacitance is 1000pF.
SERVICE Digital I/O Service pin (active LOW). 36 50
(Built-in Configurable Pull-up)
CLKSEL Digital Input Tie to VDD5. 34 48
IO0-IO3 Digital I/O Large current-sink capacity (20mA). General purpose I/O. 2, 3, 4, 5 62, 63, 64, 1
The output of timer/counter 1 may be routed to IO0.
The output of timer/counter 2 may be routed to IO1.
IO4-IO7, IO11 Digital I/O General purpose I/O. The input of timer/counter 1 may be 6, 7, 8, 9, 33 2, 3, 4, 13, 47
(Built-in Configurable Pull-up) one of IO4-IO7. The input of timer/counter 2 is IO4.
IO8 Digital I/O General purpose I/O. UART RX. SPI slave clock input. 10 14
SPI master clock output.
IO9 Digital I/O General purpose I/O. SPI slave data output. SPI master 11 15
data input.
IO10 Digital I/O General purpose I/O. SPI slave data input. SPI master 12 16
data output.
D0-D7 I/O Bi-directional data bus N/A 12, 11, 10, 9, 8, 7, 6, 5
R/W Output Read/write control output for external memory N/A 37
PL 3150 Power Line Smart Transceiver Pinout Diagram
64 Pin LQFP
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Pin Name Type Pin Functions PL 3120-E4T10 PL 3150-L10
38 TSSOP Pin No. 64 LQFP Pin No.
EOutput Enable clock control output for external memory N/A 17
A0-A15 Output Memory address output port N/A 38, 39, 40, 41, 42, 43,
44, 45, 57, 58, 60, 59,
53, 56, 55, 54
VDD5 Power Power input (5V nom). All VDD5 pins must be 13, 27, 37 18, 32, 51
connected together externally.
VDD5A Power Power input (5V nom). Supplies on-chip analog 19 24
circuitry.
GND Power Power input (0V, GND). All GND pins must be 1, 23, 28, 38 28, 33, 52, 61
connected together externally.
ICTMode Digital Input In-circuit test mode control. Driving ICTMode high and 32 46
RESET low will place all outputs in high impedance mode
for in-circuit test. Tie to GND for normal operation.
PKD Digital Output Packet Detect LED driver. 21 26
BIU Digital Output Band in Use LED driver. 22 27
RXIN Analog Input Receiver input. 15 20
INTIN,INTOUT Analog I/O Integrator input and output. 17, 18 22, 23
RXC Analog Input Receive signal. 16 21
OOGAS Analog Input Comparator to detect when energy storage power supply 14 19
lacks sufficient energy to transmit a packet. Tie to VCORE
if not used.
VCORE Power Output of internal 1.8V regulator. Requires 0.1µF 20 25
external capacitor.
TXON Digital Output High when transmitting. Used to drive LED to show 31 36
packet transmission.
TXDAC Analog Output Transmit waveform DAC output. 26 31
TXSENSE Analog Input Transmit amplifier sense feedback. 25 30
TXBIAS Analog Output Transmit amplifier bias generator. 24 29
Recommended Operating Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD5 VDD5 Supply Voltage 4.75 5.00 5.25 V
VDD5A VDD5A Supply Voltage 4.60 5.00 5.25 V
TAAmbient Temperature -40 25 85 ºC
FA-band XIN Frequency for A-band Operation 6.5523 6.5536 6.5549 MHz
(6.5536MHz ±200ppm)
FC-band XIN Frequency for C-band Operation 9.9980 10.0000 10.0020 MHz
(10.0000MHz ±200ppm)
Electrical Characteristics (over recommended operating conditions)
Symbol Parameter Min. Typ. Max. Unit
VIL Digital Input Low-Level Voltage 0.8 V
VIH Digital Input High-Level Voltage 2.0 V
VOL Digital Output Low-Level Voltage V
Iout<20µA 0.1
IO4-IO11, A0-A14, D0-D7, R/W, E (IOL = 1.4mA) 0.4
IO0-IO3, SERVICE, RESET (IOL= 20mA) 0.8
IO0-IO3, SERVICE, RESET (IOL = 10mA) 0.4
PKD, BIU, TXON (IOL= 12mA) 0.5
VOH Digital Output High-Level Voltage V
|Iout|<20µA VDD5-0.1
IO4-IO11, A0-A14, D0-D7, R/W, E (IOH = -1.4mA) VDD5-0.5
IO0-IO3, SERVICE, RESET (IOH = -1.4mA) VDD5-0.4
PKD, BIU, TXON (IOH = -12mA) VDD5-0.5
Vhys Digital Input Hysteresis 175 mV
Iin Input Current (Excluding Pull-ups)2-10 10 µA
NOTE:2 IO4-IO7 and SERVICE pins have configurable pull-ups. The RESET pin has a permanent pull-up.
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Symbol Parameter Min. Typ. Max. Unit
IpuPull-up Source Current (Vout=0, Output=High-Z)230 300 µA
IDD PL 3120 Power Line Smart Transceiver VDD5 + VDD5A Supply 9 13 mA
Current (not including I/O or internal pull-up current)
IDD PL 3150 Power Line Smart Transceiver VDD5 + VDD5A Supply 12 16 mA
Current (not including I/O or internal pull-up current)
VLVI VDD5 LVI Trip Point 4.0 4.45 V
External Memory Interface Timing - PL 3150 Power Line Smart Transceiver (over
recommended operating conditions) See Figures 1 to 6 for detailed measurement information
Parameter Description Min. Max. Unit
tcyc Memory Cycle Time 199.96 200.04 ns
(Input Clock 10MHz, +/- 200ppm)
tcyc Memory Cycle Time 305.12 305.79 ns
(Input Clock 6.5536MHz, +/- 200ppm)
PWEH Pulse Width, E High3tcyc/2-5 tcyc/2+5 ns
PWELPulse Width, E Low tcyc/2-5 tcyc/2+5 ns
tADDelay, E High to Address Valid 40 ns
tAH Address Hold Time After E High 10 ns
tRD Delay, E High to R/W Valid Read 40 ns
tRH R/W Hold Time Read After E High 10 ns
tWR Delay, E High to R/W Valid Write 40 ns
tWH R/W Hold Time Write After E High 10 ns
tDSR Read Data Setup Time to E High 20 ns
tDHR Data Hold Time Read After E High 0 ns
tDHW Data Hold Time Write After E High410 ns
tDDW Delay, E Low to Data Valid 15 ns
tacc5External Read Access Time (tacc = tcyc-tAD-tDSR) at 10MHz Input Clock 140 ns
Recommended Operating Conditions for Power Line Smart Transceiver
Discrete Interface Circuitry1
Symbol Parameter Min. Typ. Max. Unit
VARX VASupply Voltage - Receive Mode68.5 12.0 18.0 V
VATX VASupply Voltage - Transmit Mode610.8 12.0 18.0 V
TAAmbient Temperature -40 25 85 ºC
Electrical Characteristics of Power Line Smart Transceiver Discrete Interface
Circuitry1(over recommended operating conditions)
Symbol Parameter Min. Typ. Max. Unit
IARX VASupply Current - Receive Mode 350 500 µA
IATX VASupply Current - Transmit Mode 120 250 mA
VOTX Transmit Output Voltage 7 Vp-p
ITXLIM Transmit Output Current Limit 1.0 Ap-p
ZINRX Input Impedance - Receive Mode 500 Ω
(with recommended RXCOMP inductor)
ZOTX Output Impedance - Transmit Mode 0.9 Ω
VPMU Power Management - Upper VAThreshold 11.2 12.1 13.0 V
VPML Power Management - Lower VAThreshold 7.3 7.9 8.6 V
NOTES:
3tcyc = 2/f where f is the input clock (XIN) frequency (10 or 6.5536MHz).
4The data hold parameter, tDHW, is measured to disable levels shown in Figure 6, rather than to the traditional data invalid levels.
5This parameter considers only the memory read access time from address to data. This does not allow for chip enable decode. See Neuron 3150
Chip External Memory Interface Engineering Bulletin (005-0013-01D) for memory decode timing analysis examples.
6Minimum value can be 8.5V under certain conditions (refer to Data Book for details).
Maximum value must also satisfy the following: VATXAVE < (150-TAMAX)/(8*DMAX);
Where: VATXAVE = Average VA supply voltage while transmitting
TAMAX = Maximum ambient temperature (ºC)
DMAX = Maximum transmit duty cycle of the device (expressed as decimal number)
mtg; 59557 mtg; 32557 n
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Figure 1. External Memory Interface Timing Diagram
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Figure 2. Signal Loading for Timing Specifications
Figure 3. Test Point Levels for E Pulse Width Measurements
Figure 4. Drive Levels and Test Point Levels for Timing
Specifications Unless Otherwise Specified
Figure 5. Test Point Levels for
High Impedance-to-Drive Time Measurements
Figure 6. Test Point Levels for
Driven-to-High Impedance Time Measurements
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Absolute Maximum Ratings7
Ambient operating temperature -40 to 85ºC
Storage temperature -55 to 125ºC
Voltage on VDD5 and VDD5A pins with respect to GND -0.3 to 6.0V
Voltage on each pin with respect to GND8-0.3 to (VDD5 + 0.3V)
Voltage on TXBIAS, TXSENSE, OOGAS pins -0.3 to 1.89V
Maximum voltage on VCORE pin with respect to GND 1.89V
VDD5, VDD5A, or GND current per pin ±50mA
Input clamp current, IIK8(VI<0 or VI>VDD5) ±10mA
Output clamp current, IOK8 (VI<0 or VI>VDD5) ±10mA
Output current per pin5±25mA
Power dissipation 250mW
Reflow soldering temperature profile Refer to Joint Industry Standard document IPC/JEDEC J-STD-020C (July 2004)
Reflow soldering temperature 235ºC (Models 15310-1000 and 15320-960)
260ºC (Models 15311R-1000 and 15321R-960)
Recommended Pad Layout for PL 3120-E4T10
Power Line Smart Transceiver (38 TSSOP)
NOTES:
7Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation under these conditions is not implied.
8Applies to all pins except VDD5, VDD5A, VCORE, TXBIAS, TXSENSE, and OOGAS
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Recommended Pad Layout for PL 3150-L10
Power Line Smart Transceiver (64 LQFP)
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Symbol mm (prevailing dimensions) inch
Min. Nom. Max. Min. Nom. Max.
A- - 1.20 --0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.17 - 0.27 0.0067 - 0.011
c 0.09 - 0.20 0.0035 - 0.0079
D 9.60 9.70 9.80 0.378 0.381 0.385
E 6.40 BSC 0.252 BSC
e 0.50 BSC 0.0197 BSC
E1 4.30 4.40 4.50 0.169 0.173 0.177
L 0.45 0.60 0.75 0.0177 0.023 0.030
θ1 0° - -
PL 3120-E4T10 Power Line Smart Transceiver Package Diagram
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PL 3150-L10 Power Line Smart Transceiver Package Diagram
Symbol mm (prevailing dimensions) inch
Min. Nom. Max. Min. Nom. Max.
A-- 1.60 -- 0.063
A1 0.05 - 0.15 0.002 - 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.09 0.16 0.20 0.0035 0.0063 0.0079
D 12.00 BSC 0.472 BSC
D1 10.00 BSC 0.394 BSC
D3 7.50 BSC 0.295 BSC
e 0.50 BSC 0.0197 BSC
E 12.00 BSC 0.472 BSC
E1 10.00 BSC 0.394 BSC
E3 7.50 BSC 0.295 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
LI 1.00 REF 0.0394 REF
θ0º 3. 3.5º
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Ordering Information
Copyright © 2005-2006, Echelon Corporation. Echelon, LON, LonWorks, LonMark, LonBuilder, NodeBuilder, LonManager, LonTalk, LonUsers, LonPoint, Digital Home, Neuron, 3120, 3150, LNS,
i.LON, LonWorld, ShortStack, LonMaker, Panoramix, Panoramix Powered by Echelon, the Echelon logo, and the LonUsers logo are trademarks of Echelon Corporation registered in the United
States and other countries. LonLink, LonResponse, LonSupport, LONews, Open Systems Alliance, OpenLDV, Powered by Echelon, LNS Powered by Echelon, LonWorks Powered by Echelon,
Networked Energy Services Powered by Echelon, NES Powered by Echelon, and Digital Home Powered by Echelon are trademarks of Echelon Corporation. Other trademarks belong to their
respective holders.
Disclaimer
Neuron Chips, Smart Transceivers, and other OEM Products were not designed for use in equipment or systems which involve danger to human health or safety or a risk of property damage and
Echelon assumes no responsibility or liability for use of the Neuron Chips or Smart Transceivers in such applications. ECHELON MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS,
EXPRESS, IMPLIED, STATUTORY OR IN ANY COMMUNICATION WITH YOU, AND ECHELON SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE. 003-0378-01H
Power Line Smart
Transceiver IC
Product Number
Model
Number
RoHS Com-
pliant
Maximum
Input
Clock
EEPROM RAM ROM
External
Memory In-
terface
IC
Package
PL DSK Develop-
ment Support Kit
Model Number
PL 3120-E4T10 15310-1000 No 10MHz 4K Bytes 2K Bytes 24K Bytes No 38 TSSOP 17050R-21-27
PL 3150-L10 15320-960 No 10MHz 0.5K Bytes 2K Bytes N/A Yes 64 LQFP 17050R-21-27
PL 3120-E4T10 15311R-1000 Yes 10MHz 4K Bytes 2K Bytes 24K Bytes No 38 TSSOP 17050R-21-27
PL 3150-L10 15321R-960 Yes 10MHz 0.5K Bytes 2K Bytes N/A Yes 64 LQFP 17050R-21-27
Documentation
The PL 3120 / PL 3150 Power Line Smart Transceiver Data Book may be downloaded from Echelon’s web site or ordered through
Echelon’s literature fulfillment department.
Document Echelon Part Number
PL 3120 / PL 3150 Power Line Smart Transceiver Data Book 005-0154-01