EPC2038 Datasheet by EPC

RoHS (A @ Halogen-Free 2038 eGaNm FETs are supplied onlyi ivaked die form wikh solder bumps.
eGaN® FET DATASHEET EPC2038
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
EPC2038 – Enhancement Mode Power Transistor
with Integrated Reverse Gate Clamp Diode
VDS , 100 V
RDS(on) , 3300 mΩ
ID , 0.5 A
EPC2038 eGaN® FETs are supplied only in
passivated die form with solder bumps.
Die size: 0.9 mm x 0.9 mm
Applications
Synchronous Bootstrap for:
• High Speed DC-DC Conversion
• Wireless Power Transfer
• High Frequency Hard-Switching and
Soft-Switching Circuits
• Lidar/Pulsed Power Applications
• Class-D Audio
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
D
S
G
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 100 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120
ID
Continuous (TA = 25°C, RθJA = 100°C/W) 0.5 A
Pulsed (25°C, TPULSE = 300 µs) 0.5
VGS Gate-to-Source Voltage 6 V
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 27
°C/W RθJB Thermal Resistance, Junction-to-Board 91
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 100
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 μA 100 V
IDSS Drain-Source Leakage VDS = 80 V, VGS = 0 V 20 100 μA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25˚C 0.0001 0.5 mA
Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125˚C 0.002 1
VFSource-Gate Forward Voltage IF = 0.2 mA, VDS = 0 V 2.7 V
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.1 mA 0.8 1.7 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.05 A 2100 3300 mΩ
VSD Source-Drain Forward Voltage IS = 0.1 A, VGS = 0 V 2.9 V
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET EPC2038
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0.5
0.4
0.3
0.2
0.1
00 0.5 1.0 1.5 2.0 2.5 3.0
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
2.5 3.0 3.5 4.0 4.5 5.0
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 0.05 A
ID = 0.10 A
ID = 0.15 A
ID = 0.20 A
8000
6000
4000
2000
0
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
0.5
0.4
0.3
0.2
0.1
0
2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 0.05 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
8000
6000
4000
2000
0
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance
VDS = 50 V, VGS = 0 V
7 8.4
pF
CRSS
Reverse Transfer Capacitance
0.02
COSS
Output Capacitance
1.6 2.4
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 50 V, VGS = 0 V 2.2
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
2.7
RG
Gate Resistance
4.8 Ω
QG
Total Gate Charge
VDS = 50 V, VGS = 5 V, ID = 0.05 A 44
pC
QGS
Gate-to-Source Charge
VDS = 50 V, ID = 0.05 A
20
QGD
Gate-to-Drain Charge
4
QG(TH)
Gate Charge at Threshold
18
QOSS
Output Charge
VDS = 50 V, VGS = 0 V 134
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2038
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All measurements were done with substrate shortened to source.
Capacitance (pF)
100
10
1
0.1
0.01
0.001 0 20 40 60 80 100
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
0.5
0.4
0.3
0.2
0.1
0
25˚C
125˚C
VGS = 0 V
Figure 9: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 0.1 mA
Capacitance (pF)
0 20 40 60 80 100
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
0 10 20 30 40 50
Figure 6: Gate Charge
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (pC)
ID = 0.05 A
VDS = 50 V
Figure 8: Normalized On-State Resistance vs. Temperature
ID = 0.05 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
“—L— J: “‘L— fl
eGaN® FET DATASHEET EPC2038
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Figure 10: Transient Thermal Response Curves
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
0.2
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Case
PDM
t1
t2
1
0.1
0.01
0.001
0.0001
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
10-6 10-5 10-4 10-3 10-2 10-1 1
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.1
0.02
0.05
Single Pulse
0.01
Duty Cycle:
Junction-to-Board
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
Figure 11: Safe Operating Area
0.01
0.1
1
0.1 1 10 100
I
D
– Drain Current (A)
V
DS
- Drain Voltage (V)
Limited by R
DS(on)
Pulse Width
100 ms
10 ms
1 ms
eGaN® FET DATASHEET EPC2038
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DIE MARKINGS
AD
YYY
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7”reel
7” reel
a
d e f g
c
b
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
DIM Dimension (mm)
EPC2038 (Note 1) Target MIN MAX
a8.00 7.90 8.30
b1.75 1.65 1.85
c (Note 2) 3.50 3.45 3.55
d4.00 3.90 4.10
e4.00 3.90 4.10
f (Note 2) 2.00 1.95 2.05
g1.50 1.50 1.60
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
EPC2038 AD YYY
Die orientation dot
Gate Pad bump is
under this corner
AD
YYY
M ‘ you In ‘ a ,7 9w ‘
eGaN® FET DATASHEET EPC2038
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RECOMMENDED
LAND PATTERN
(measurements in µm)
DIE OUTLINE
Solder Bump View
Side View
RECOMMENDED
STENCIL DRAWING
(measurements in µm)
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Pads 1 is Gate;
Pad 3 is Drain;
Pads 2, 4 are Source
The land pattern is solder mask defined
Solder mask is 10 μm smaller per side than bump
Recommended stencil should be 4 mil (100 µm) thick, must be
laser cut, openings per drawing.
Intended for use with SAC305 Type 4 solder,reference 88.5%
metals content.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
DIM MIN Nominal MAX
A870 900 930
B870 900 930
c450 450 450
d450 450 450
e210 225 240
f210 225 240
g187 208 229
(625)
Seating Plane
815 Max
165+/- 17
B
A
ce
31
24
g
d
f
Pads 1 is Gate;
Pad 3 is Drain;
Pads 2, 4 are Source
900
900
450
225
42
13
200 +20 / - 10 (*)
X4
242
450
225
* minimum 190
450 225
250
900
900
450
225
R60
Information subject to change
without notice.
Revised December, 2020