Settings
Fast Delivery
Free Shipping
Incoterms
Payment Types
Marketplace Product
ESD207-B1-02 Series Datasheet by Infineon Technologies
(in/fineon
Power Management & Multimarket
Data Sheet
Revision 1.3, 2013-12-19
Final
ESD207-B1-02 Series
Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes
ESD207-B1-02ELS
ESD207-B1-02EL
TVS Diode
Transient Voltage Suppressor Diodes
@neon
ESD207-B1-02 Series
FinalData Sheet 2 Revision 1.3, 2013-12-19
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,
CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,
MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,
PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,
SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2010-10-26
Revision History: Revision 1.2, 2013-11-15
Page or Item Subjects (major changes since previous revision)
Revision 1.3, 2013-12-19
5 Table 2-2) updated
Infineon
Y 7
ESD207-B1-02 Series
Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes
FinalData Sheet 3 Revision 1.3, 2013-12-19
1 Ultra Low Clamping Bi-directional ESD / Transient / Surge
Protection Diodes
1.1 Features
• ESD / transient / surge protection of one data / Vbus line exceding standard:
–IEC61000-4-2 (ESD): ±30 kV (air / contact discharge)
–IEC61000-4-4 (EFT): ±50 A (5/50 ns)
–IEC61000-4-5 (surge): ±8 A (8/20 μs)
• Bi-directional, symmetrical working voltage up to VRWM =±3.3V
• Medium capacitance: CL= 14 pF (typ.)
• Ultra low clamping voltage VCL =7V (typ.) @ IPP =16A (TLP)
• Ultra low dynamic resistance RDYN =0.13Ω typ.
• Pb-free (RoHS compliant) and halogen free package
1.2 Application Examples
• Audio Line, Speaker, Headset, Microphone Protection
• Human Interface Devices (Keyboard, Touchpad, Buttons)
1.3 Product Description
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1 Ordering Information
Type Package Configuration Marking code
ESD207-B1-02ELS TSSLP-2-3 1 line, bi-directional Y
ESD207-B1-02EL TSLP-2-19 1 line, bi-directional A
a) Pin configuration
PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_S chematicDiag.vsd
b) Schematic diagram
TSLP-2
TSSLP -2
Pin 1 Pin 2
Pin 1 Pin 2 Pin 1
Pin 2
Pin 1 marking
(lasered)
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 4 Revision 1.3, 2013-12-19
2 Characteristics
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
2.1 Electrical Characteristics at TA= 25 °C, unless otherwise specified
Figure 2-1 Definitions of electrical characteristics
Table 2-1 Maximum Ratings at TA = 25 °C, unless otherwise specified1)
1) Device is electrically symmetrical
Parameter Symbol Values Unit
Min. Typ. Max.
ESD contact discharge2)
2) VESD according to IEC61000-4-2
VESD ––30kV
Peak pulse current (tp = 8/20 μs)3)
3) IPP according to IEC61000-4-5
IPP ––8A
Peak pulse power (tp = 8/20 μs)3) PPK ––65W
Operating temperature range TOP -40 – 125 °C
Storage temperature Tstg -65 – 150 °C
!"#
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 5 Revision 1.3, 2013-12-19
Table 2-2 DC Characteristics at TA = 25 °C, unless otherwise specified1)
1) Device is electrically symmetrical
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Reverse working voltage VRWM ––3.3V
Reverse current IR– – 50 nA VR=3.3V
Trigger voltage Vt1 3.65 – – V
Holding voltage Vh3.65 4.4 – V IR=10mA
Table 2-3 AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Line capacitance CL–1420pFVR = 0 V, f = 1 MHz
Table 2-4 ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Clamping voltage1) Pin 1 to GND
1) ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP
conditions: Z0=50Ω, tp= 100 ns, tr,
=0.6ns, ITLP and VTLP averaging window: t1= 30 ns to t2= 60 ns, extraction of
dynamic resistance using least squares fit of TLP characteristic between ITLP1 = 5 A and ITLP2 = 40 A. Please refer to
Application Note AN210 [1]
VCL –7–VITLP =16A
–9– ITLP =30A
Clamping voltage1) GND to Pin 1 – 7.5 – ITLP =16A
–9– ITLP =30A
Clamping voltage2)
2) IPP according to IEC61000-4-5 (tp= 8/20 µs)
–4.55.8 IPP =1A
–6.88.1 IPP =8A
Dynamic resistance1) RDYN –0.13–Ω
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 6 Revision 1.3, 2013-12-19
2.2 Typical Characteristics at TA = 25 °C, unless otherwise specified
Figure 2-2 Reverse current: IR=f(VR)
Figure 2-3 Reverse current: IR=f(TA), VR=3.3V
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
-4 -3 -2 -1 0 1 2 3 4
IR [A]
VR [V]
0.1
1
10
100
1000
-50 -25 0 25 50 75 100 125
IR [nA]
TA [°C]
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 7 Revision 1.3, 2013-12-19
Figure 2-4 Line capacitance: CL=f(VR), f=1MHz
5
10
15
20
-4 -3 -2 -1 0 1 2 3 4
CL [pF]
VR [V]
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 8 Revision 1.3, 2013-12-19
Figure 2-5 Clamping voltage (TLP): ITLP =f(VTLP) according ANSI/ESD STM5.5.1 - Electrostatic Discharge
Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0=50Ω,
tp=100ns, tr=0.6ns, ITLP and VTLP averaging window: t1=ns to t2= 60 ns, extraction of
dynamic resistance using squares fit to TLP characteristics between ITLP1 = 5 A and
ITLP2 = 40 A. Please refer to Application Note AN210 [1]
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
-20 -15 -10 -5 0 5 10 15 20
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
ITLP [A]
Equivalent VIEC [kV]
VTLP [V]
ESD207-B1-02series
RDYN
RDYN = 0.13 Ω
RDYN = 0.14 Ω
I
I
/
II
@ineon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 9 Revision 1.3, 2013-12-19
Figure 2-6 Pulse current (IEC61000-4-5) versus clamping voltage: IPP =f(VCL)
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
-15 -10 -5 0 5 10 15
IPP [A]
VCL [V]
ESD207-B1-02series
RDYN
RDYN = 0.3 Ω
RDYN = 0.4 Ω
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 10 Revision 1.3, 2013-12-19
Figure 2-7 IEC61000-4-2 : VCL =f(t), 8 kV positive pulse from pin 1 to pin 2
Figure 2-8 IEC61000-4-2 : VCL =f(t), 8 kV negative pulse from pin 1 to pin 2
-10
0
10
20
30
40
-100 0 100 200 300 400 500 600 700 800 900
VCL [V]
tp [ns]
VCL-max-peak = 38.1 [V]
VCL-30ns-peak = 7.7 [V]
-40
-30
-20
-10
0
10
-100 0 100 200 300 400 500 600 700 800 900
VCL [V]
tp [ns]
VCL-max-peak = -37.5 [V]
VCL-30ns-peak = -6.9 [V]
@neon
ESD207-B1-02 Series
Characteristics
FinalData Sheet 11 Revision 1.3, 2013-12-19
Figure 2-9 IEC61000-4-2 : VCL =f(t), 15 kV positive pulse from pin 1 to pin 2
Figure 2-10 IEC61000-4-2 : VCL =f(t), 15 kV negative pulse from pin 1 to pin 2
-30
-20
-10
0
10
20
30
40
50
60
70
-100 0 100 200 300 400 500 600 700 800 900
VCL [V]
tp [ns]
VCL-max-peak = 61.3 [V]
VCL-30ns-peak = 8.3 [V]
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
-100 0 100 200 300 400 500 600 700 800 900
VCL [V]
tp [ns]
VCL-max-peak = -65.0 [V]
VCL-30ns-peak = -7.6 [V]
@neon
c Audio out ‘ -
single ended l \
ESD207-B1-02 Series
Application Information
FinalData Sheet 12 Revision 1.3, 2013-12-19
3 Application Information
Figure 3-1 Single line, bi-directional ESD / Transient protection
Audio Amp.
Audio_out
single ended
Audio_in Headset
cable
Headset con.
e.g. 3.5mm jack
ESD Diode
ESD-strike ESD-strike
Headset
Ear-phone
Time
Voltage
+Vcc
-Vcc
Charge
Pump
+Vcc
PCB line
ESD3V 3S1B-02LS_A pplication.vsd
infineon
m ‘
/ 4»\
ESD207-B1-02 Series
Package Information
FinalData Sheet 13 Revision 1.3, 2013-12-19
4 Package Information
4.1 TSSLP-2-3
Figure 4-1 TSSLP-2-3: Package overview (dimension in mm)
Figure 4-2 TSSLP-2-3: Footprint (dimension in mm)
Figure 4-3 TSSLP-2-3: Tape information (dimension in mm)
Figure 4-4 TSSLP-2-3: Marking (example)
TSSLP-2-3, -4-PO V01
±0.05
0.32
1
2
±0.035
0.2
1)
0.62
±0.05
+0.01
0.31-0.02
1) Dimension applies to plated terminals
Cathode
marking
1)
±0.035
0.26
0.05 MAX.
Bottom viewTop view
0.355
0.27
0.19
0.19
0.19
Copper Solder mask Stencil apertures
0.57
0.24
0.62
0.32
0.24
0.14
TSSLP-2-3, -4-FP V02
Ex
4
Ey
0.35
Cathode
marking
8
g
TSSLP-2-3, -4-TP V03
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Ex Ey
Punched Tape
Tape type
Embossed Tape
0.43 0.73
0.37 0.67
TSSLP-2-3, -4-MK V01
Cathode marking
1
Type code
infineon
ESD207-B1-02 Series
Package Information
FinalData Sheet 14 Revision 1.3, 2013-12-19
4.2 TSLP-2-19
Figure 4-5 TSLP-2-19: Package outline(dimension in mm), proposal
Figure 4-6 TSLP-2-19: Footprint (dimension in mm), proposal
Figure 4-7 TSLP-2-19: Tape information (dimension in mm), proposal
Figure 4-8 TSLP-2-19: Marking (example)
TSLP-2-19, -20-PO V01
±0.05
0.6
1
2
±0.05
0.65
±0.035
0.25 1)
1±0.05
0.05 MAX.
+0.01
0.31-0.02
1) Dimension applies to plated terminals
Cathode
marking
1)
±0.035
0.5
Bottom viewTop view
TSLP-2-19, -20-FP V01
0.45
0.28
0.28
0.38
0.93
Copper Solder mask Stencil apertures
0.35
1
0.6
0.35
0.3
0.76
4
1.16
0.4
Cathode
marking
8
TSLP-2-19, -20-TP V02
Type code
Cathode marking
TSLP-2-19, -20-MK V01
12
infineon
ESD207-B1-02 Series
References
FinalData Sheet 15 Revision 1.3, 2013-12-19
References
[1] Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
