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Spartan-3E FPGA Family

Xilinx Inc.

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DS312 December 14, 2018 www.xilinx.com
Product Specification 1
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Module 1:
Introduction and Ordering Information
DS312 (v4.2) December 14, 2018
Introduction
•Features
Architectural Overview
Package Marking
Ordering Information
Module 2:
Functional Description
DS312 (v4.2) December 14, 2018
Input/Output Blocks (IOBs)
Overview
SelectIO™ Signal Standards
Configurable Logic Block (CLB)
•Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Powering Spartan®-3E FPGAs
Production Stepping
Module 3:
DC and Switching Characteristics
DS312 (v4.2) December 14, 2018
DC Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
Switching Characteristics
I/O Timing
SLICE Timing
•DCM Timing
Block RAM Timing
Multiplier Timing
Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312 (v4.2) December 14, 2018
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
1Spartan-3E FPGA Family
Data Sheet
DS312 December 14, 2018 Product Specification
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 2
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Introduction
The Spartan®-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic
applications. The five-member family offers densities
ranging from 100,000 to 1.6 million system gates, as shown
in Table 1.
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of
configuration. These Spartan-3E FPGA enhancements,
combined with advanced 90 nm process technology, deliver
more functionality and bandwidth per dollar than was
previously possible, setting new standards in the
programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection, and digital television
equipment.
The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
Up to 376 I/O pins or 156 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
622+ Mb/s data transfer rate per I/O
True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL
differential I/O
Enhanced Double Data Rate (DDR) support
DDR SDRAM support up to 333 Mb/s
Abundant, flexible logic resources
Densities up to 33,192 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
Up to 648 Kbits of fast block RAM
Up to 231 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 300 MHz)
Eight global clocks plus eight additional clocks per each half
of device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
Complete Xilinx ISE® and WebPACK™ software
MicroBlaze™ and PicoBlaze embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in
some devices)
Low-cost QFP and BGA packaging options
Common footprints support easy density migration
Pb-free packaging options
XA Automotive version available
8Spartan-3E FPGA Family:
Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 Product Specification
Table 1: Summary of Spartan-3E FPGA Attributes
Device System
Gates
Equivalent
Logic Cells
CLB Array
(One CLB = Four Slices) Distributed
RAM bits(1)
Block
RAM
bits(1)
Dedicated
Multipliers DCMs Maximum
User I/O
Maximum
Differential
I/O Pairs
Rows Columns Total
CLBs
Total
Slices
XC3S100E 100K 2,160 22 16 240 960 15K 72K 4 2 108 40
XC3S250E 250K 5,508 34 26 612 2,448 38K 216K 12 4 172 68
XC3S500E 500K 10,476 46 34 1,164 4,656 73K 360K 20 4 232 92
XC3S1200E 1200K 19,512 60 46 2,168 8,672 136K 504K 28 8 304 124
XC3S1600E 1600K 33,192 76 58 3,688 14,752 231K 648K 36 8 376 156
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 3
Architectural Overview
The Spartan-3E family architecture consists of five
fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
X-Ref Target - Figure 1
Figure 1: Spartan-3E Family Architecture
Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 4
Configuration
Spartan-3E FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
Furthermore, Spartan-3E FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
I/O Capabilities
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination.
Spartan-3E FPGAs support the following single-ended
standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices, 66 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Spartan-3E FPGAs support the following differential
standards:
•LVDS
Bus LVDS
• mini-LVDS
•RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
Footprint
Size (mm) 16x16 8x8 22x22 30.5x30.5 17x17 19x19 21x21 23x23
Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
XC3S100E 66(2)
9(7)
30
(2)
83
(11)
35
(2)
108
(28)
40
(4) - - - - - - - - - -
XC3S250E 66
(7)
30
(2)
92
(7)
41
(2)
108
(28)
40
(4)
158
(32)
65
(5)
172
(40)
68
(8) - - - - - -
XC3S500E 66(3)
(7)
30
(2)
92
(7)
41
(2) - - 158
(32)
65
(5)
190
(41)
77
(8)
232
(56)
92
(12) - - - -
XC3S1200E - - - - - - - - 190
(40)
77
(8)
250
(56)
99
(12)
304
(72)
124
(20) - -
XC3S1600E - - - - - - - - - - 250
(56)
99
(12)
304
(72)
124
(20)
376
(82)
156
(21)
Notes:
1. All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4, Pinout Descriptions.
2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
3. The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 5
Package Marking
Figure 2 provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
On the QFP and BGA packages, the optional numerical
Stepping Code follows the Lot Code.
The “5C” and “4I” part combinations can have a dual mark
of “5C/4I”. Devices with a single mark are only guaranteed
for the marked speed grade and temperature range. All “5C
and “4I” part combinations use the Stepping 1 production
silicon.
X-Ref Target - Figure 2
Figure 2: Spartan-3E QFP Package Marking Example
X-Ref Target - Figure 3
Figure 3: Spartan-3E BGA Package Marking Example
X-Ref Target - Figure 4
Figure 4: Spartan-3E CP132 and CPG132 Package Marking Example
Stepping Code (optional)
Date Code
Mask Revision Code
Process Technology
XC3S250E
TM
PQ208AGQ0525
D1234567A
4C
SPARTAN
Device Type
Package
Speed Grade
Temperature Range
Fabrication Code
Pin P1
R
R
DS312-1_06_102905
Lot Code
Lot Code
Date Code
XC3S250E
TM
4C
SPARTAN
Device Type
BGA Ball A1
Package
Speed Grade
Temperature Range
R
R
DS312-1_02_090105
FT256AGQ0525
D1234567A
Mask Revision Code
Process Code
Fabrication Code
Stepping Code
(optional)
Date Code
Temperature Range
Speed Grade
3S250E
C5AGQ 4C
Device Type
Ball A1
Lot Code
Package
C5 = CP132
C6 = CPG132
Mask Revision Code Fabrication Code
DS312-1_05_032105
F1234567-0525
PHILIPPINES
Process Code
Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 6
Ordering Information
Spartan-3E FPGAs are available in both standard and
Pb-free packaging options for all device/package
combinations. All devices are available in Pb-free packages,
which adds a ‘G’ character to the ordering code. All devices
are available in either Commercial (C) or Industrial (I)
temperature ranges. Both the standard –4 and faster –5
speed grades are available for the Commercial temperature
range. However, only the –4 speed grade is available for the
Industrial temperature range. See Table 2 for valid
device/package combinations.
Production Stepping
The Spartan-3E FPGA family uses production stepping to
indicate improved capabilities or enhanced features.
Stepping 1 is, by definition, a functional superset of
Stepping 0. Furthermore, configuration bitstreams
generated for any stepping are forward compatible. See
Table 72 for additional details.
Xilinx has shipped both Stepping 0 and Stepping 1. Designs
operating on the Stepping 0 devices perform similarly on a
Stepping 1 device. Stepping 1 devices have been shipping
since 2006. The faster speed grade (-5), Industrial (I grade),
Automotive devices, and -4C devices with date codes 0901
(2009) and later, are always Stepping 1 devices. Only -4C
devices have shipped as Stepping 0 devices.
To specify only the later stepping for the -4C, append an S#
suffix to the standard ordering code, where # is the stepping
number, as indicated in Table 3.
The stepping level is optionally marked on the device using
a single number character, as shown in Figure 2, Figure 3,
and Figure 4.
Device Speed Grade Package Type / Number of Pins Temperature Range (TJ)
XC3S100E -4
Standard Performance
VQ100
VQG100
100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)
XC3S250E -5 High Performance(1) CP132
CPG132
132-ball Chip-Scale Package (CSP) I Industrial (–40°C to 100°C)
XC3S500E(2) TQ144
TQG144
144-pin Thin Quad Flat Pack (TQFP)
XC3S1200E PQ208
PQG208
208-pin Plastic Quad Flat Pack (PQFP)
XC3S1600E FT256
FTG256
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FG320
FGG320
320-ball Fine-Pitch Ball Grid Array (FBGA)
FG400
FGG400
400-ball Fine-Pitch Ball Grid Array (FBGA)
FG484
FGG484
484-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
2. The XC3S500E VQG100 is available only in the -4 Speed Grade.
3. See DS635 for the XA Automotive Spartan-3E FPGAs.
XC3S250E -4 FT 256 C
Device Type
Speed Grade Temperature Range
Package Type
Example:
DS312_03_082409
S1 (optional code to specify Stepping 1)
Number of Pins
Table 3: Spartan-3E Optional Stepping Level Ordering
Stepping
Number Suffix Code Status
0 None or S0 Production
1 S1 Production
Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 7
Revision History
The following table shows the revision history for this document.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
Date Version Revision
03/01/2005 1.0 Initial Xilinx release.
03/21/2005 1.1 Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs for CP132
package. Added package markings for QFP packages (Figure 2) and CP132/CPG132 packages
(Figure 4).
11/23/2005 2.0 Added differential HSTL and SSTL I/O standards. Updated Table 2 to indicate number of input-only
pins. Added Production Stepping information, including example top marking diagrams.
03/22/2006 3.0 Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and updated I/O
counts for the XC3S1600E in FG320 package (Table 2). Added information about dual markings for –
5C and –4I product combinations to Package Marking.
11/09/2006 3.4 Added 66 MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that Stepping
1 parts are Production status. Promoted Module 1 to Production status. Synchronized all modules to
v3.4.
04/18/2008 3.7 Added XC3S500E VQG100 package. Added reference to XA Automotive version. Updated links.
08/26/2009 3.8 Added paragraph to Configuration indicating the device supports MultiBoot configuration. Added
package sizes to Table 2. Described the speed grade and temperature range guarantee for devices
having a single mark in paragraph 3 under Package Marking. Deleted Pb-Free Packaging example
under Ordering Information. Revised information under Production Stepping. Revised description of
Table 3.
10/29/2012 4.0 Added Notice of Disclaimer. This product is not recommended for new designs.
Updated Table 2 footprint size of PQ208.
07/19/2013 4.1 Removed banner. This product IS recommended for new designs.
12/14/2018 4.2 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 8
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 9
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Design Documentation Available
The functionality of the Spartan®-3E FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-Distributed RAM
-SRL16 Shift Registers
-Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools
•IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User
Guide
Configuration Overview
-Configuration Pins and Behavior
-Bitstream Sizes
Detailed Descriptions by Mode
-Master Serial Mode using Xilinx® Platform
Flash PROM
-Master SPI Mode using Commodity SPI Serial
Flash PROM
-Master BPI Mode using Commodity Parallel
NOR Flash PROM
-Slave Parallel (SelectMAP) using a Processor
-Slave Serial using a Processor
-JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Xilinx Alerts
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
Sign Up for Alerts on Xilinx.com
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Spartan-3E FPGA Starter Kit
For specific hardware examples, please see the Spartan-3E
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
Spartan-3E FPGA Starter Kit Board page
http://www.xilinx.com/s3estarter
UG230: Spartan-3E FPGA Starter Kit User Guide
114 Spartan-3E FPGA Family:
Functional Description
DS312 (v4.2) December 14, 2018 Product Specification
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 10
Introduction
As described in Architectural Overview, the Spartan-3E
FPGA architecture consists of five fundamental functional
elements:
Input/Output Blocks (IOBs)
Configurable Logic Block (CLB) and Slice Resources
Block RAM
Dedicated Multipliers
Digital Clock Managers (DCMs)
The following sections provide detailed information on each
of these functions. In addition, this section also describes
the following functions:
Clocking Infrastructure
Interconnect
Configuration
Powering Spartan-3E FPGAs
Input/Output Blocks (IOBs)
For additional information, refer to the “Using I/O
Resources” chapter in UG331.
IOB Overview
The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package
pin and the FPGA’s internal logic. The IOB is similar to that
of the Spartan-3 family with the following differences:
Input-only blocks are added
Programmable input delays are added to all blocks
DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full
IOB capabilities. Thus there are no connections or logic for
an output path. The following paragraphs assume that any
reference to output functionality does not apply to the
input-only blocks. The number of input-only blocks varies
with device size, but is never more than 25% of the total IOB
count.
Figure 5 is a simplified diagram of the IOB’s internal
structure. There are three main signal paths within the IOB:
the output path, input path, and 3-state path. Each path has
its own pair of storage elements that can act as either
registers or latches. For more information, see Storage
Element Functions. The three main signal paths are as
follows:
The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line. After
the delay element, there are alternate routes through a
pair of storage elements to the IQ1 and IQ2 lines. The
IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal
logic. The delay element can be set to ensure a hold
time of zero (see Input Delay Functions).
The output path, starting with the O1 and O2 lines,
carries data from the FPGA’s internal logic through a
multiplexer and then a three-state driver to the IOB
pad. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements.
The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
the FPGA’s internal logic through a multiplexer to the
output driver. In addition to this direct path, the
multiplexer provides the option to insert a pair of
storage elements.
All signal paths entering the IOB, including those
associated with the storage elements, have an inverter
option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 11
X-Ref Target - Figure 5
Figure 5: Simplified IOB Diagram
TFF1
Three-state Path
T
T1
TCE
T2
TFF2
Q
SR
DDR
MUX
REV
Q
SR REV
OFF1
Output Path
O1
OCE
O2
OFF2
Q
SR
DDR
MUX
Keeper
Latch
VCCO
V
REF
Pin
I/O Pin
from
Adjacent
IOB
DS312-2_19_110606
I/O
Pin
Program-
mable
Output
Driver
ESDPull-Up
Pull-
Down ESD
REV
Q
SR REV
OTCLK1
OTCLK2
IFF1
Input Path
IDDRIN1
I
ICE
IFF2
Q
SR
Programmable
DelayLVCMOS, LVTTL, PCI
Single-ended Standards
using VREF
Differential Standards
REV
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
Q
SR REV
IDDRIN2
ICLK1
ICLK2
SR
REV
IQ1
IQ2
Programmable
Delay
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 12
Input Delay Functions
Each IOB has a programmable delay block that optionally
delays the input signal. In Figure 6, the signal path has a
coarse delay element that can be bypassed. The input
signal then feeds a 6-tap delay line. The coarse and tap
delays vary; refer to timing reports for specific delay values.
All six taps are available via a multiplexer for use as an
asynchronous input directly into the FPGA fabric. In this
way, the delay is programmable in 12 steps. Three of the six
taps are also available via a multiplexer to the D inputs of
the synchronous storage elements. The delay inserted in
the path to the storage element can be varied in six steps.
The first, coarse delay element is common to both
asynchronous and synchronous paths, and must be either
used or not used for both paths.
The delay values are set up in the silicon once at
configuration time—they are non-modifiable in device
operation.
The primary use for the input delay element is to adjust the
input delay path to ensure that there is no hold time
requirement when using the input flip-flop(s) with a global
clock. The default value is chosen automatically by the
Xilinx software tools as the value depends on device size
and the specific device edge where the flip-flop resides. The
value set by the Xilinx ISE software is indicated in the Map
report generated by the implementation tools, and the
resulting effects on input timing are reported using the
Timing Analyzer tool.
If the design uses a DCM in the clock path, then the delay
element can be safely set to zero because the
Delay-Locked Loop (DLL) compensation automatically
ensures that there is still no input hold time requirement.
Both asynchronous and synchronous values can be
modified, which is useful where extra delay is required on
clock or data inputs, for example, in interfaces to various
types of RAM.
These delay values are defined through the
IBUF_DELAY_VALUE and the IFD_DELAY_VALUE
parameters. The default IBUF_DELAY_VALUE is 0,
bypassing the delay elements for the asynchronous input.
The user can set this parameter to 0-12. The default
IFD_DELAY_VALUE is AUTO. IBUF_DELAY_VALUE and
IFD_DELAY_VALUE are independent for each input. If the
same input pin uses both registered and non-registered
input paths, both parameters can be used, but they must
both be in the same half of the total delay (both either
bypassing or using the coarse delay element).
X-Ref Target - Figure 6
Figure 6: Programmable Fixed Input Delay Elements
PA D
Asynchronous input (I)
Synchronous input (IQ2)
Synchronous input (IQ1)
DQ
DQ
UG331_c10_09_011508
Coarse Delay
IBUF_DELAY_VALUE
IFD_DELAY_VALUE
Spartan-3E FPGA Family: Functional Description
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Product Specification 13
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element pair on either the Output path or the
Three-State path can be used together with a special
multiplexer to produce Double-Data-Rate (DDR)
transmission. This is accomplished by taking data
synchronized to the clock signal’s rising edge and
converting it to bits synchronized on both the rising and the
falling edge. The combination of two registers and a
multiplexer is referred to as a Double-Data-Rate D-type
flip-flop (ODDR2).
Table 4 describes the signal paths associated with the
storage element.
As shown in Figure 5, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE
controls the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 5.
Table 4: Storage Element Signal Description
Storage
Element
Signal
Description Function
D Data input Data at this input is stored on the active edge of CK and enabled by CE. For latch operation when
the input is enabled, data passes directly to the output Q.
Q Data output The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q mirrors the data at D.
CK Clock input Data is loaded into the storage element on this input’s active edge with CE asserted.
CE Clock Enable input When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
SR Set/Reset input This input forces the storage element into the state specified by the SRHIGH/SRLOW attributes.
The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
If both SR and REV are active at the same time, the storage element gets a value of 0.
REV Reverse input This input is used together with SR. It forces the storage element into the state opposite from what
SR does. The SYNC/ASYNC attribute setting determines whether the REV input is synchronized
to the clock or not. If both SR and REV are active at the same time, the storage element gets a
value of 0.
Table 5: Storage Element Options
Option Switch Function Specificity
FF/Latch Chooses between an edge-triggered flip-flop or a
level-sensitive latch
Independent for each storage element
SYNC/ASYNC Determines whether the SR set/reset control is
synchronous or asynchronous
Independent for each storage element
SRHIGH/SRLOW Determines whether SR acts as a Set, which forces
the storage element to a logic 1 (SRHIGH) or a
Reset, which forces a logic 0 (SRLOW)
Independent for each storage element, except when using
ODDR2. In the latter case, the selection for the upper
element will apply to both elements.
INIT1/INIT0 When Global Set/Reset (GSR) is asserted or after
configuration this option specifies the initial state of
the storage element, either set (INIT1) or reset
(INIT0). By default, choosing SRLOW also selects
INIT0; choosing SRHIGH also selects INIT1.
Independent for each storage element, except when using
ODDR2, which uses two IOBs. In the ODDR2 case,
selecting INIT0 for one IOBs applies to both elements
within the IOB, although INIT1 could be selected for the
elements in the other IOB.
Spartan-3E FPGA Family: Functional Description
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Product Specification 14
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the
technique of synchronizing signals to both the rising and
falling edges of the clock signal. Spartan-3E devices use
register pairs in all three IOB paths to perform DDR
operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a
special multiplexer to form a DDR D-type flip-flop (ODDR2).
This primitive permits DDR transmission where output data
bits are synchronized to both the rising and falling edges of
a clock. DDR operation requires two clock signals (usually
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as
shown in Figure 7. The Digital Clock Manager (DCM)
generates the two clock signals by mirroring an incoming
signal, and then shifting it 180 degrees. This approach
ensures minimal skew between the two signals.
Alternatively, the inverter inside the IOB can be used to
invert the clock signal, thus only using one clock line and
both rising and falling edges of that clock line as the two
clocks for the DDR flip-flops.
The storage-element pair on the Three-State path (TFF1
and TFF2) also can be combined with a local multiplexer to
form a DDR primitive. This permits synchronizing the output
enable to both the rising and falling edges of a clock. This
DDR operation is realized in the same way as for the output
path.
The storage-element pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register, and the inverted clock
signal triggers the other register. The registers take turns
capturing bits of the incoming DDR data signal. The
primitive to allow this functionality is called IDDR2.
Aside from high bandwidth data transfers, DDR outputs also
can be used to reproduce, or mirror, a clock signal on the
output. This approach is used to transmit clock and data
signals together (source synchronously). A similar
approach is used to reproduce a clock signal at multiple
outputs. The advantage for both approaches is that skew
across the outputs is minimal.
Register Cascade Feature
In the Spartan-3E family, one of the IOBs in a differential
pair can cascade its input storage elements with those in
the other IOB as part of a differential pair. This is intended to
make DDR operation at high speed much simpler to
implement. The new DDR connections that are available
are shown in Figure 5 (dashed lines), and are only available
for routing between IOBs and are not accessible to the
FPGA fabric. Note that this feature is only available when
using the differential I/O standards LVDS, RSDS, and
MINI_LVDS.
IDDR2
As a DDR input pair, the master IOB registers incoming
data on the rising edge of ICLK1 (= D1) and the rising edge
of ICLK2 (= D2), which is typically the same as the falling
edge of ICLK1. This data is then transferred into the FPGA
fabric. At some point, both signals must be brought into the
same clock domain, typically ICLK1. This can be difficult at
high frequencies because the available time is only one half
of a clock cycle assuming a 50% duty cycle. See Figure 8
for a graphical illustration of this function.
X-Ref Target - Figure 7
Figure 7: Two Methods for Clocking the DDR Register
DS312-2_20_021105
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
180˚ 0˚
Q
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
Q
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 15
In the Spartan-3E device, the signal D2 can be cascaded
into the storage element of the adjacent slave IOB. There it
is re-registered to ICLK1, and only then fed to the FPGA
fabric where it is now already in the same time domain as
D1. Here, the FPGA fabric uses only the clock ICLK1 to
process the received data. See Figure 9 for a graphical
illustration of this function.
ODDR2
As a DDR output pair, the master IOB registers data coming
from the FPGA fabric on the rising edge of OCLK1 (= D1)
and the rising edge of OCLK2 (= D2), which is typically the
same as the falling edge of OCLK1. These two bits of data
are multiplexed by the DDR mux and forwarded to the
output pin. The D2 data signal must be re-synchronized
from the OCLK1 clock domain to the OCLK2 domain using
FPGA slice flip-flops. Placement is critical at high
frequencies, because the time available is only one half a
clock cycle. See Figure 10 for a graphical illustration of this
function.
The C0 or C1 alignment feature of the ODDR2 flip-flop,
originally introduced in the Spartan-3E FPGA family, is not
recommended or supported in the ISE development
software. The ODDR2 flip-flop without the alignment feature
remains fully supported. Without the alignment feature, the
ODDR2 feature behaves equivalent to the ODDR flip-flop
on previous Xilinx FPGA families.
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that
support a wide range of I/O signaling standards (Table 6
and Table 7). The majority of the I/Os also can be used to
form differential pairs to support any of the differential
signaling standards (Table 7).
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to the Xilinx Software Manuals and
Help.
X-Ref Target - Figure 8
Figure 8: Input DDR (without Cascade Feature)
X-Ref Target - Figure 9
Figure 9: Input DDR Using Spartan-3E Cascade Feature
DQ
ICLK1
To Fabric
PAD
D1
D2
PAD
ICLK2
DQ
ICLK1
ICLK2
DQIQ2 IDDRIN2
D1
D2 d-1 d+1 d+3 d+5 d+7
d d+2 d+4 d+6 d+8
d d+8d+7d+6d+5d+4d+3d+2d+1
DS312-2_22_030105
X-Ref Target - Figure 10
Figure 10: Output DDR
DQ
OCLK1
From
Fabric
PAD
D2
D1
d+4d+3d+2d+1d
PAD
OCLK1
D1
D2
OCLK2
DQ
OCLK2
DS312-2_23_030105
d+1 d+3 d+5 d+7
dd+2 d+4 d+6
d+8
d+9
d+8 d+10
d+5 d+6 d+7
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 16
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. For a
particular VCCO voltage, Table 6 and Table 7 list all of the
IOSTANDARDs that can be combined and if the
IOSTANDARD is supported as an input only or can be used
for both inputs and outputs.
Table 6: Single-Ended IOSTANDARD Bank Compatibility
Single-Ended
IOSTANDARD
VCCO Supply/Compatibility Input Requirements
1.2V 1.5V 1.8V 2.5V 3.3V VREF
Board
Termination
Voltage (VTT)
LVTTL ----Input/
Output N/R(1) N/R
LVCMOS33 ----Input/
Output N/R N/R
LVCMOS25 ---Input/
Output Input N/R N/R
LVCMOS18 - - Input/
Output Input Input N/R N/R
LVCMOS15 -Input/
Output Input Input Input N/R N/R
LVCMOS12 Input/
Output Input Input Input Input N/R N/R
PCI33_3 ----Input/
Output N/R N/R
PCI66_3 ----Input/
Output N/R N/R
HSTL_I_18 - - Input/
Output Input Input 0.9 0.9
HSTL_III_18 - - Input/
Output Input Input 1.1 1.8
SSTL18_I - - Input/
Output Input Input 0.9 0.9
SSTL2_I ---Input/
Output Input 1.25 1.25
Notes:
1. N/R - Not required for input operation.
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 17
HSTL and SSTL inputs use the Reference Voltage (VREF) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to VREF
inputs. For banks that do not contain HSTL or SSTL, VREF
pins remain available for user I/Os or input pins.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling
properties (for example, Common-Mode Rejection) of these
standards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards. A
unique L-number, part of the pin name, identifies the
line-pairs associated with each bank (see Module 4, Pinout
Descriptions). For each pair, the letters P and N designate
the true and inverted lines, respectively. For example, the
pin names IO_L43P_3 and IO_L43N_3 indicate the true
and inverted lines comprising the line pair L43 on Bank 3.
VCCO provides current to the outputs and additionally
powers the On-Chip Differential Termination. VCCO must be
2.5V when using the On-Chip Differential Termination. The
VREF lines are not required for differential operation.
To further understand how to combine multiple
IOSTANDARDs within a bank, refer to IOBs Organized into
Banks, page 19.
On-Chip Differential Termination
Spartan-3E devices provide an on-chip ~120Ω differential
termination across the input differential receiver terminals.
The on-chip input differential termination in Spartan-3E
devices potentially eliminates the external 100Ω termination
resistor commonly found in differential receiver circuits.
Differential termination is used for LVDS, mini-LVDS, and
RSDS as applications permit.
On-chip Differential Termination is available in banks with
VCCO = 2.5V and is not supported on dedicated input pins.
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = "<TRUE/FALSE>";
Table 7: Differential IOSTANDARD Bank Compatibility
Differential
IOSTANDARD
VCCO Supply Input
Requirements:
VREF
Differential Bank
Restriction(1)
1.8V 2.5V 3.3V
LVDS_25 Input
Input,
On-chip Differential Termination,
Output
Input
VREF is not used for
these I/O standards
Applies to Outputs
Only
RSDS_25 Input
Input,
On-chip Differential Termination,
Output
Input Applies to Outputs
Only
MINI_LVDS_25 Input
Input,
On-chip Differential Termination,
Output
Input Applies to Outputs
Only
LVPECL_25 Input Input Input
No Differential Bank
Restriction
(other I/O bank
restrictions might
apply)
BLVDS_25 Input Input,
Output Input
DIFF_HSTL_I_18 Input,
Output Input Input
DIFF_HSTL_III_18 Input,
Output Input Input
DIFF_SSTL18_I Input,
Output Input Input
DIFF_SSTL2_I Input Input,
Output Input
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 18
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O or Input-only pin to a determined state.
Pull-up and pull-down resistors are commonly applied to
unused I/Os, inputs, and three-state outputs, but can be
used on any I/O or Input-only pin. The pull-up resistor
connects an IOB to VCCO through a resistor. The resistance
value depends on the VCCO voltage (see Module 3, DC and
Switching Characteristics for the specifications). The
pull-down resistor similarly connects an IOB to ground with
a resistor. The PULLUP and PULLDOWN attributes and
library primitives turn on these optional resistors.
By default, PULLDOWN resistors terminate all unused I/O
and Input-only pins. Unused I/O and Input-only pins can
alternatively be set to PULLUP or FLOAT. To change the
unused I/O Pad setting, set the Bitstream Generator
(BitGen) option UnusedPin to PULLUP, PULLDOWN, or
FLOAT. The UnusedPin option is accessed through the
Properties for Generate Programming File in ISE. See
Bitstream Generator (BitGen) Options.
During configuration a Low logic level on the HSWAP pin
activates pull-up resistors on all I/O and Input-only pins not
actively used in the selected configuration mode.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 12) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 8.
To adjust the drive strength for each output, the DRIVE
attribute is set to the desired drive strength: 2, 4, 6, 8, 12,
and 16. Unless otherwise specified in the FPGA application,
the software default IOSTANDARD is LVCMOS25, SLOW
slew rate, and 12 mA output drive.
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
X-Ref Target - Figure 11
Figure 11: Differential Inputs and Outputs
100Ω
~120Ω
Spartan-3E
Differential Input
Z0 = 50Ω
Z0 = 50Ω
Spartan-3E
Differential
Output
Spartan-3E
Differential Input
with On-Chip
Differential
Terminator
Z0 = 50Ω
Z0 = 50Ω
Spartan-3E
Differential
Output
DS312-2_24_082605
X-Ref Target - Figure 12
Figure 12: Keeper Circuit
Table 8: Programmable Output Drive Current
IOSTANDARD Output Drive Current (mA)
2 4 6 8 12 16
LVTTL ✔✔✔✔✔✔
LVCMOS33 ✔✔✔✔✔✔
LVCMOS25 ✔✔✔✔✔ -
LVCMOS18 ✔✔✔✔ - -
LVCMOS15 ✔✔✔ - - -
LVCMOS12 - - - - -
Pull-up
Pull-down
Input Path
Output Path
Keeper
DS312-2_25_020807
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 19
IOBs Organized into Banks
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 13. Each bank maintains
separate VCCO and VREF supplies. The separate supplies
allow each bank to independently set VCCO. Similarly, the
VREF supplies can be set for each bank. Refer to Table 6
and Table 7 for VCCO and VREF requirements.
When working with Spartan-3E devices, most of the
differential I/O standards are compatible and can be
combined within any given bank. Each bank can support
any two of the following differential standards: LVDS_25
outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As
an example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential
termination are a valid combination. A combination not
allowed is a single bank with LVDS_25 outputs, RSDS_25
outputs, and MINI_LVDS_25 outputs.
I/O Banking Rules
When assigning I/Os to banks, these VCCO rules must be
followed:
1. All VCCO pins on the FPGA must be connected even if a
bank is unused.
2. All VCCO lines associated within a bank must be set to
the same voltage level.
3. The VCCO levels used by all standards assigned to the
I/Os of any given bank must agree. The Xilinx
development software checks for this. Table 6 and
Table 7 describe how different standards use the VCCO
supply.
4. If a bank does not have any VCCO requirements,
connect VCCO to an available voltage, such as 2.5V or
3.3V. Some configuration modes might place additional
VCCO requirements. Refer to Configuration for more
information.
If any of the standards assigned to the Inputs of the bank
use VREF, then the following additional rules must be
observed:
1. All VREF pins must be connected within a bank.
2. All VREF lines associated with the bank must be set to
the same voltage level.
3. The VREF levels used by all standards assigned to the
Inputs of the bank must agree. The Xilinx development
software checks for this. Table 6 describes how different
standards use the VREF supply.
If VREF is not required to bias the input switching thresholds,
all associated VREF pins within the bank can be used as
user I/Os or input pins.
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in
Module 4, Pinout Descriptions. In some cases, there are
subtle differences between devices available in the same
footprint. These differences are outlined for each package,
such as pins that are unconnected on one device but
connected on another in the same package or pins that are
dedicated inputs on one package but full I/O on another.
When designing the printed circuit board (PCB), plan for
potential future upgrades and package migration.
The Spartan-3E family is not pin-compatible with any
previous Xilinx FPGA family.
Dedicated Inputs
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the
differential Dedicated Inputs, the on-chip differential
termination is not available. To replace the on-chip
differential termination, choose a differential pair that
supports outputs (IO_Lxxx_x) or use an external 100Ω
termination resistor on the board.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
extends P-to-N from the pad to VCCO and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes
limits the ability of Spartan-3E I/Os to tolerate high signal
voltages. The VIN absolute maximum rating in Table 73 of
Module 3, DC and Switching Characteristics specifies the
voltage range that I/Os can tolerate.
X-Ref Target - Figure 13
Figure 13: Spartan-3E I/O Banks (top view)
DS312-2_26_021205
Bank 0
Bank 2
Bank 3
Bank 1
Spartan-3E FPGA Family: Functional Description
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Product Specification 20
Supply Voltages for the IOBs
The IOBs are powered by three supplies:
1. The VCCO supplies, one for each of the FPGA’s I/O
banks, power the output drivers. The voltage on the
VCCO pins determines the voltage swing of the output
signal.
2. VCCINT is the main power supply for the FPGA’s internal
logic.
3. VCCAUX is an auxiliary source of power, primarily to
optimize the performance of various FPGA functions
such as I/O switching.
I/O and Input-Only Pin Behavior During
Power-On, Configuration, and User Mode
In this section, all behavior described for I/O pins also
applies to input-only pins and dual-purpose I/O pins that are
not actively involved in the currently-selected configuration
mode.
All I/O pins have ESD clamp diodes to their respective VCCO
supply and from GND, as shown in Figure 5. The VCCINT
(1.2V), VCCAUX (2.5V), and VCCO supplies can be applied in
any order. Before the FPGA can start its configuration
process, VCCINT, VCCO Bank 2, and VCCAUX must have
reached their respective minimum recommended operating
levels indicated in Table 74. At this time, all output drivers
are in a high-impedance state. VCCO Bank 2, VCCINT, and
VCCAUX serve as inputs to the internal Power-On Reset
circuit (POR).
A Low level applied to the HSWAP input enables pull-up
resistors on user-I/O and input-only pins from power-on
throughout configuration. A High level on HSWAP disables
the pull-up resistors, allowing the I/Os to float. HSWAP
contains an internal pull-up resistor and defaults to High if
left floating. As soon as power is applied, the FPGA begins
initializing its configuration memory. At the same time, the
FPGA internally asserts the Global Set-Reset (GSR), which
asynchronously resets all IOB storage elements to a default
Low state. Also see Pin Behavior During Configuration.
Upon the completion of initialization and the beginning of
configuration, INIT_B goes High, sampling the M0, M1, and
M2 inputs to determine the configuration mode.
Configuration data is then loaded into the FPGA. The I/O
drivers remain in a high-impedance state (with or without
pull-up resistors, as determined by the HSWAP input)
throughout configuration.
At the end of configuration, the GSR net is released, placing
the IOB registers in a Low state by default, unless the
loaded design reverses the polarity of their respective SR
inputs.
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the
beginning of design operation in the User mode. After the
GTS net is released, all user I/Os go active while all unused
I/Os are pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
Behavior of Unused I/O Pins After
Configuration
By default, the Xilinx ISE development software
automatically configures all unused I/O pins as input pins
with individual internal pull-down resistors to GND.
This default behavior is controlled by the UnusedPin
bitstream generator (BitGen) option, as described in
Table 69.
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing
compatible with IEEE 1149.1/1532 standards. During
boundary-scan operations such as EXTEST and HIGHZ the
pull-down resistor is active. See JTAG Mode for more
information on programming via JTAG.
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 21
Configurable Logic Block (CLB) and
Slice Resources
For additional information, refer to the “Using Configurable
Logic Blocks (CLBs)” chapter in UG331.
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to
implement logic and two dedicated storage elements that
can be used as flip-flops or latches. The LUTs can be used
as a 16x1 memory (RAM16) or as a 16-bit shift register
(SRL16), and additional multiplexers and carry logic simplify
wide logic and arithmetic functions. Most general-purpose
logic in a design is automatically mapped to the slice
resources in the CLBs. Each CLB is identical, and the
Spartan-3E family CLB structure is identical to that for the
Spartan-3 family.
CLB Array
The CLBs are arranged in a regular array of rows and
columns as shown in Figure 14.
Each density varies by the number of rows and columns of
CLBs (see Table 9).
Slices
Each CLB comprises four interconnected slices, as shown
in Figure 16. These slices are grouped in pairs. Each pair is
organized as a column with an independent carry chain.
The left pair supports both logic and memory functions and
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
LUTs support both logic and memory (including both
RAM16 and SRL16 shift registers) while half support logic
only, and the two types alternate throughout the array
columns. The SLICEL reduces the size of the CLB and
lowers the cost of the device, and can also provide a
performance advantage over the SLICEM.
X-Ref Target - Figure 14
Figure 14: CLB Locations
DS312-2_31_021205
Spartan-3E
FPGA
X0Y1 X1Y1
X0Y0 X1Y0
IOBs
CLB Slice
X2Y1 X3Y1
X2Y0 X3Y0
X0Y3 X1Y3
X0Y2 X1Y2
X2Y3 X3Y3
X2Y2 X3Y2
Table 9: Spartan-3E CLB Resources
Device CLB
Rows
CLB
Columns
CLB
Total(1) Slices LUTs /
Flip-Flops
Equivalent
Logic Cells
RAM16 /
SRL16
Distributed
RAM Bits
XC3S100E 22 16 240 960 1,920 2,160 960 15,360
XC3S250E 34 26 612 2,448 4,896 5,508 2,448 39,168
XC3S500E 46 34 1,164 4,656 9,312 10,476 4,656 74,496
XC3S1200E 60 46 2,168 8,672 17,344 19,512 8,672 138,752
XC3S1600E 76 58 3,688 14,752 29,504 33,192 14,752 236,032
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Figure 1 in Module 1).
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 22
.
X-Ref Target - Figure 15
Figure 15: Simplified Diagram of the Left-Hand SLICEM
WF[4:1]
DS312-2_32_042007
D
DI
DIWS
Notes:
1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
2. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has
an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 23
Slice Location Designations
The Xilinx development software designates the location of
a slice according to its X and Y coordinates, starting in the
bottom left corner, as shown in Figure 14. The letter ‘X’
followed by a number identifies columns of slices,
incrementing from the left side of the die to the right. The
letter ‘Y’ followed by a number identifies the position of each
slice in a pair as well as indicating the CLB row,
incrementing from the bottom of the die. Figure 16 shows
the CLB located in the lower left-hand corner of the die. The
SLICEM always has an even ‘X’ number, and the SLICEL
always has an odd ‘X’ number.
Slice Overview
A slice includes two LUT function generators and two
storage elements, along with additional logic, as shown in
Figure 17.
Both SLICEM and SLICEL have the following elements in
common to provide logic, arithmetic, and ROM functions:
Two 4-input LUT function generators, F and G
Two storage elements
Two wide-function multiplexers, F5MUX and FiMUX
Carry and arithmetic logic
X-Ref Target - Figure 16
Figure 16: Arrangement of Slices within the CLB
DS099-2_05_082104
Interconnect
to Neighbors
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
CIN
SLICE
X0Y1
SLICE
X0Y0
Switch
Matrix
COUT
CLB
COUT
SHIFTOUT
SHIFTIN
CIN
SLICE
X1Y1
SLICE
X1Y0
X-Ref Target - Figure 17
Figure 17: Resources in a Slice
FiMUX
F5MUX
Register
Carry
Carry Register
Arithmetic Logic
SLICEM SLICEL
SRL16
RAM16
LUT4 (G)
SRL16
RAM16
LUT4 (F)
FiMUX
F5MUX
Register
Carry
Carry Register
Arithmetic Logic
LUT4 (G)
LUT4 (F)
DS312-2_13_020905
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 24
The SLICEM pair supports two additional functions:
Two 16x1 distributed RAM blocks, RAM16
Two 16-bit shift registers, SRL16
Each of these elements is described in more detail in the
following sections.
Logic Cells
The combination of a LUT and a storage element is known
as a “Logic Cell”. The additional features in a slice, such as
the wide multiplexers, carry logic, and arithmetic gates, add
to the capacity of a slice, implementing logic that would
otherwise require additional LUTs. Benchmarks have
shown that the overall slice is equivalent to 2.25 simple logic
cells. This calculation provides the equivalent logic cell
count shown in Table 9.
Slice Details
Figure 15 is a detailed diagram of the SLICEM. It represents
a superset of the elements and connections to be found in
all slices. The dashed and gray lines (blue when viewed in
color) indicate the resources found only in the SLICEM and
not in the SLICEL.
Each slice has two halves, which are differentiated as top
and bottom to keep them distinct from the upper and lower
slices in a CLB. The control inputs for the clock (CLK), Clock
Enable (CE), Slice Write Enable (SLICEWE1), and
Reset/Set (RS) are shared in common between the two
halves.
The LUTs located in the top and bottom portions of the slice
are referred to as “G” and “F”, respectively, or the “G-LUT
and the “F-LUT”. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively.
Each slice has two multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. Depending
on the slice, the FiMUX takes on the name F6MUX,
F7MUX, or F8MUX, according to its position in the
multiplexer chain. The lower SLICEL and SLICEM both
have an F6MUX. The upper SLICEM has an F7MUX, and
the upper SLICEL has an F8MUX.
The carry chain enters the bottom of the slice as CIN and
exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
CY0G and CYMUXG in the top portion. The dedicated
arithmetic logic includes the exclusive-OR gates XORF and
XORG (bottom and top portions of the slice, respectively)
as well as the AND gates FAND and GAND (bottom and top
portions, respectively).
See Table 10 for a description of all the slice input and
output signals.
Table 10: Slice Inputs and Outputs
Name Location Direction Description
F[4:1] SLICEL/M Bottom Input F-LUT and FAND inputs
G[4:1] SLICEL/M Top Input G-LUT and GAND inputs or Write Address (SLICEM)
BX SLICEL/M Bottom Input Bypass to or output (SLICEM) or storage element, or control input to F5MUX,
input to carry logic, or data input to RAM (SLICEM)
BY SLICEL/M Top Input Bypass to or output (SLICEM) or storage element, or control input to FiMUX,
input to carry logic, or data input to RAM (SLICEM)
BXOUT SLICEM Bottom Output BX bypass output
BYOUT SLICEM Top Output BY bypass output
ALTDIG SLICEM Top Input Alternate data input to RAM
DIG SLICEM Top Output ALTDIG or SHIFTIN bypass output
SLICEWE1 SLICEM Common Input RAM Write Enable
F5 SLICEL/M Bottom Output Output from F5MUX; direct feedback to FiMUX
FXINA SLICEL/M Top Input Input to FiMUX; direct feedback from F5MUX or another FiMUX
FXINB SLICEL/M Top Input Input to FiMUX; direct feedback from F5MUX or another FiMUX
Fi SLICEL/M Top Output Output from FiMUX; direct feedback to another FiMUX
CE SLICEL/M Common Input FFX/Y Clock Enable
SR SLICEL/M Common Input FFX/Y Set or Reset or RAM Write Enable (SLICEM)
CLK SLICEL/M Common Input FFX/Y Clock or RAM Clock (SLICEM)
SHIFTIN SLICEM Top Input Data input to G-LUT RAM
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Product Specification 25
Main Logic Paths
Central to the operation of each slice are two nearly
identical data paths at the top and bottom of the slice. The
description that follows uses names associated with the
bottom path. (The top path names appear in parentheses.)
The basic path originates at an interconnect switch matrix
outside the CLB. See Interconnect for more information on
the switch matrix and the routing connections.
Four lines, F1 through F4 (or G1 through G4 on the upper
path), enter the slice and connect directly to the LUT. Once
inside the slice, the lower 4-bit path passes through a LUT
‘F’ (or ‘G’) that performs logic operations. The LUT Data
output, ‘D’, offers five possible paths:
1. Exit the slice via line “X” (or “Y”) and return to
interconnect.
2. Inside the slice, “X” (or “Y”) serves as an input to the
DXMUX (or DYMUX) which feeds the data input, “D”, of
the FFX (or FFY) storage element. The “Q” output of the
storage element drives the line XQ (or YQ) which exits
the slice.
3. Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
4. With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on “X” (or “Y”).
5. Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The “D” outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
BY in the top half) can take any of several possible
branches:
1. Bypass both the LUT and the storage element, and
then exit the slice as BXOUT (or BYOUT) and return to
interconnect.
2. Bypass the LUT, and then pass through a storage
element via the D input before exiting as XQ (or YQ).
3. Control the wide function multiplexer F5MUX (or
FiMUX).
4. Via multiplexers, serve as an input to the carry chain.
5. Drive the DI input of the LUT.
6. BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Functions.
7. Finally, the DIG_MUX multiplexer can switch BY onto
the DIG line, which exits the slice.
The control inputs CLK, CE, SR, BX and BY have
programmable polarity. The LUT inputs do not need
programmable polarity because their function can be
inverted inside the LUT.
The sections that follow provide more detail on individual
functions of the slice.
Look-Up Tables
The Look-Up Table or LUT is a RAM-based function
generator and is the main resource for implementing logic
functions. Furthermore, the LUTs in each SLICEM pair can
be configured as Distributed RAM or a 16-bit shift register,
as described later.
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). Any four-variable
Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by
cascading LUTs or by using the wide function multiplexers
that are described later.
The output of the LUT can connect to the wide multiplexer
logic, the carry and arithmetic logic, or directly to a CLB
output or to the CLB storage element. See Figure 18.
SHIFTOUT SLICEM Bottom Output Shift data output from F-LUT RAM
CIN SLICEL/M Bottom Input Carry chain input
COUT SLICEL/M Top Output Carry chain output
X SLICEL/M Bottom Output Combinatorial output
Y SLICEL/M Top Output Combinatorial output
XB SLICEL/M Bottom Output Combinatorial output from carry or F-LUT SRL16 (SLICEM)
YB SLICEL/M Top Output Combinatorial output from carry or G-LUT SRL16 (SLICEM)
XQ SLICEL/M Bottom Output FFX output
YQ SLICEL/M Top Output FFY output
Table 10: Slice Inputs and Outputs (Cont’d)
Name Location Direction Description
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Product Specification 26
Wide Multiplexers
For additional information, refer to the “Using Dedicated
Multiplexers” chapter in UG331.
Wide-function multiplexers effectively combine LUTs in
order to permit more complex logic operations. Each slice
has two of these multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. The
F5MUX multiplexes the two LUTs in a slice. The FiMUX
multiplexes two CLB inputs which connect directly to the
F5MUX and FiMUX results from the same slice or from
other slices. See Figure 19.
Depending on the slice, FiMUX takes on the name F6MUX,
F7MUX, or F8MUX. The designation indicates the number
of inputs possible without restriction on the function. For
example, an F7MUX can generate any function of seven
inputs. Figure 20 shows the names of the multiplexers in
each position in the Spartan-3E CLB. The figure also
includes the direct connections within the CLB, along with
the F7MUX connection to the CLB below.
Each mux can create logic functions of more inputs than
indicated by its name. The F5MUX, for example, can
generate any function of five inputs, with four inputs
duplicated to two LUTs and the fifth input controlling the
mux. Because each LUT can implement independent 2:1
muxes, the F5MUX can combine them to create a 4:1 mux,
which is a six-input function. If the two LUTs have
completely independent sets of inputs, some functions of all
nine inputs can be implemented. Table 11 shows the
connections for each multiplexer and the number of inputs
possible for different types of functions.
X-Ref Target - Figure 18
Figure 18: LUT Resources in a Slice
A[4:1]
F[4:1] 4
4
DS312-2_33_111105
F-LUT
G[4:1] D
A[4:1] YQ
Y
G-LUT
FFY
FFX
DXQ
X
X-Ref Target - Figure 19
Figure 19: Dedicated Multiplexers in Spartan-3E CLB
FiMUX
FX (Local Feedback to FXIN)
Y (General Interconnect)
YQ
0
1
0
1
FXINA
FXINB
F[4:1]
G[4:1]
DQ
F5MUX
BY
BX
F5 (Local Feedback to FXIN)
X (General Interconnect)
XQ
DQ
LUT
LUT
x312-2_34_021205
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 27
X-Ref Target - Figure 20
Figure 20: MUXes and Dedicated Feedback in Spartan-3E CLB
DS312-2_38_021305
F5
F8
F5
F6
F5
F7
F5
F6
F5
FX
F5
FX
F5
X
FXINA
FXINB
FXINA
FXINB
FXINA
FXINB
FXINA
FXINB
F5
FX
Table 11: MUX Capabilities
MUX Usage Input Source
Total Number of Inputs per Function
For Any Function For MUX For Limited
Functions
F5MUX F5MUX LUTs 5 6 (4:1 MUX) 9
FiMUX F6MUX F5MUX 6 11 (8:1 MUX) 19
F7MUX F6MUX 7 20 (16:1 MUX) 39
F8MUX F7MUX 8 37 (32:1 MUX) 79
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DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 28
The wide multiplexers can be used by the automatic tools or
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described in
Figure 21, Table 12, and Table 13. The description is similar
for the F6MUX, F7MUX, and F8MUX. Each has versions
with a general output, local output, or both.
X-Ref Target - Figure 21
Figure 21: F5MUX with Local and General Outputs
Table 12: F5MUX Inputs and Outputs
Signal Function
I0 Input selected when S is Low
I1 Input selected when S is High
S Select input
LO Local Output that connects to the F5 or FX CLB pins,
which use local feedback to the FXIN inputs to the
FiMUX for cascading
O General Output that connects to the general-purpose
combinatorial or registered outputs of the CLB
Table 13: F5MUX Function
Inputs Outputs
SI0I1 O LO
01X1 1
00X0 0
1X1 1 1
1X0 0 0
O
I0
I1
0
1
S
LO
DS312-2_35_021205
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 29
Carry and Arithmetic Logic
For additional information, refer to the “Using Carry and
Arithmetic Logic” chapter in UG331.
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and
multiplexers of the carry and arithmetic logic can also be
used for general-purpose logic, including simple wide
Boolean functions.
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers,
typically at two bits per slice. See Figure 22 and Table 14.
X-Ref Target - Figure 22
Figure 22: Carry Logic
Table 14: Carry Logic Functions
Function Description
CYINIT Initializes carry chain for a slice. Fixed selection of:
· CIN carry input from the slice below
· BX input
CY0F Carry generation for bottom half of slice. Fixed selection of:
· F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
· FAND gate for multiplication
· BX input for carry initialization
· Fixed 1 or 0 input for use as a simple Boolean function
CY0F
CYSELF
1
XORF
D
A[4:1]
F[4:1]
4CYMUXF
CYINIT
XB
XQ
X
0
1
CIN DS312-2_14_021305
FAND
F1 F2
BX
F-LUT
FFX
G[4:1]
CY0G
CYSELG
1
XORG
D
A[4:1] CYMUXG
YB
COUT
YQ
Y
0
1
GAND
G1 G2
BY
G-LUT
FFY
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 30
The basic usage of the carry logic is to generate a half-sum
in the LUT via an XOR function, which generates or
propagates a carry out COUT via the carry mux CYMUXF
(or CYMUXG), and then complete the sum with the
dedicated XORF (or XORG) gate and the carry input CIN.
This structure allows two bits of an arithmetic function in
each slice. The CYMUXF (or CYMUXG) can be instantiated
using the MUXCY element, and the XORF (or XORG) can
be instantiated using the XORCY element.
The FAND (or GAND) gate is used for partial product
multiplication and can be instantiated using the MULT_AND
component. Partial products are generated by two-input
AND gates and then added. The carry logic is efficient for
the adder, but one of the inputs must be outside the LUT as
shown in Figure 23.
The FAND (or GAND) gate is used to duplicate one of the
partial products, while the LUT generates both partial
products and the XOR function, as shown in Figure 24.
CY0G Carry generation for top half of slice. Fixed selection of:
· G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
· GAND gate for multiplication
· BY input for carry initialization
· Fixed 1 or 0 input for use as a simple Boolean function
CYMUXF Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
· CYINIT carry propagation (CYSELF = 1)
· CY0F carry generation (CYSELF = 0)
CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:
· CYMUXF carry propagation (CYSELG = 1)
· CY0G carry generation (CYSELG = 0)
CYSELF Carry generation or propagation select for bottom half of slice. Fixed selection of:
· F-LUT output (typically XOR result)
· Fixed 1 to always propagate
CYSELG Carry generation or propagation select for top half of slice. Fixed selection of:
· G-LUT output (typically XOR result)
· Fixed 1 to always propagate
XORF Sum generation for bottom half of slice. Inputs from:
·F-LUT
· CYINIT carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
XORG Sum generation for top half of slice. Inputs from:
·G-LUT
· CYMUXF carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
FAND Multiplier partial product for bottom half of slice. Inputs:
· F-LUT F1 input
· F-LUT F2 input
Result is sent through CY0F to become the carry generate signal into CYMUXF
GAND Multiplier partial product for top half of slice. Inputs:
· G-LUT G1 input
· G-LUT G2 input
Result is sent through CY0G to become the carry generate signal into CYMUXG
Table 14: Carry Logic Functions (Cont’d)
Function Description
X-Ref Target - Figure 23
Figure 23: Using the MUXCY and XORCY in the Carry
Logic
XORCY
LUT
MUXCY
B
A
Sum
CIN
DS312-2_37_021305
COUT
Spartan-3E FPGA Family: Functional Description
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Product Specification 31
The MULT_AND is useful for small multipliers. Larger
multipliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
Storage Elements
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch,
provides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively. FFY has a fixed multiplexer on the D input
selecting either the combinatorial output Y or the bypass
signal BY. FFX selects between the combinatorial output X
or the bypass signal BX.
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All
signals have programmable polarity; the default active-High
function is described.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
X-Ref Target - Figure 24
Figure 24: Using the MULT_AND for Multiplication in
Carry Logic
Bn+1
Am
Bn
Am+1
Pm+1
CIN DS312-2_39_021305
COUT
LUT
MULT_AND
Table 15: Storage Element Signals
Signal Description
D Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High during the
Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate enable (GE) are High and R
and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The
data on the Q output of the latch remains unchanged as long as G or GE remains Low.
Q Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
C Clock for edge-triggered flip-flops.
G Gate for level-sensitive latches.
CE Clock Enable for flip-flops.
GE Gate Enable for latches.
S Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the Low-to-High
clock (C) transition. A latch output is immediately set, output High.
R Synchronous Reset (Q = Low); has precedence over Set.
PRE Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
SR CLB input for R, S, CLR, or PRE
REV CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
X-Ref Target - Figure 25
Figure 25: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
FDRSE
DQ
CE
C
R
S
DS312-2_40_021305
Table 16: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
Inputs Outputs
RSCEDC Q
1 X X X 0
01X X 1
000XX No Change
00111
00100
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Product Specification 32
Initialization
The CLB storage elements are initialized at power-up,
during configuration, by the global GSR signal, and by the
individual SR or REV inputs to the CLB. The storage
elements can also be re-initialized using the GSR input on
the STARTUP_SPARTAN3E primitive. See Global Controls
(STARTUP_SPARTAN3E).
Distributed RAM
For additional information, refer to the “Using Look-Up
Tables as Distributed RAM” chapter in UG331.
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One SLICEM
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or
G[4:1] become the address lines labeled A[4:1] in the
device model and A[3:0] in the design components,
providing a 16x1 configuration in one LUT. Multiple SLICEM
LUTs can be combined in various ways to store larger
amounts of data, including 16x4, 32x2, or 64x1
configurations in one CLB. The fifth and sixth address lines
required for the 32-deep and 64-deep configurations,
respectively, are implemented using the BX and BY inputs,
which connect to the write enable logic for writing and the
F5MUX and F6MUX for reading.
Writing to distributed RAM is always synchronous to the
SLICEM clock (WCLK for distributed RAM) and enabled by
the SLICEM SR input which functions as the active-High
Write Enable (WE). The read operation is asynchronous,
and, therefore, during a write, the output initially reflects the
old data at the address being written.
The distributed RAM outputs can be captured using the
flip-flops within the SLICEM element. The WE write-enable
control for the RAM and the CE clock-enable control for the
flip-flop are independent, but the WCLK and CLK clock
inputs are shared. Because the RAM read operation is
asynchronous, the output data always reflects the currently
addressed RAM location.
A dual-port option combines two LUTs so that memory
access is possible from two independent data lines. The
same data is written to both 16x1 memories but they have
independent read address lines and outputs. The dual-port
function is implemented by cascading the G-LUT address
lines, which are used for both read and write, to the F-LUT
write address lines (WF[4:1] in Figure 15), and by
cascading the G-LUT data input D1 through the DIF_MUX
in Figure 15 and to the D1 input on the F-LUT. One CLB
provides a 16x1 dual-port memory as shown in Figure 26.
Any write operation on the D input and any read operation
on the SPO output can occur simultaneously with and
independently from a read operation on the second
read-only port, DPO.
Table 17: Slice Storage Element Initialization
Signal Description
SR Set/Reset input. Forces the storage element into the
state specified by the attribute SRHIGH or SRLOW.
SRHIGH forces a logic 1 when SR is asserted.
SRLOW forces a logic 0. For each slice, set and reset
can be set to be synchronous or asynchronous.
REV Reverse of Set/Reset input. A second input (BY)
forces the storage element into the opposite state.
The reset condition is predominant over the set
condition if both are active. Same
synchronous/asynchronous setting as for SR.
GSR Global Set/Reset. GSR defaults to active High but can
be inverted by adding an inverter in front of the GSR
input of the STARTUP_SPARTAN3E element. The
initial state after configuration or GSR is defined by a
separate INIT0 and INIT1 attribute. By default, setting
the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
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Product Specification 33
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
The global write enable signal, GWE, is asserted
automatically at the end of device configuration to enable all
writable elements. The GWE signal guarantees that the
X-Ref Target - Figure 26
Figure 26: RAM16X1D Dual-Port Usage
D
A[3:0]
WE
WCLK
SPO
DPO
DPRA[3:0]
16x1
LUT
RAM
(Read/
Write)
16x1
LUT
RAM
(Read
Only)
Optional
Register
Optional
Register
SLICEM
DS312-2_41_021305
X-Ref Target - Figure 27
Figure 27: Dual-Port RAM Component
Table 18: Dual-Port RAM Function
Inputs Outputs
WE (mode) WCLK D SPO DPO
0 (read) XX data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) D D data_d
1 (read) X data_a data_d
Notes:
1. data_a = word addressed by bits A3-A0.
2. data_d = word addressed by bits DPRA3-DPRA0.
RAM16X1D
WE SPO
D
WCLK
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3
DPO
DS312-2_42_021305
Table 19: Distributed RAM Signals
Signal Description
WCLK The clock is used for synchronous writes. The
data and the address input pins have setup
times referenced to the WCLK pin. Active on
the positive edge by default with built-in
programmable polarity.
WE The enable pin affects the write functionality of
the port. An inactive Write Enable prevents
any writing to memory cells. An active Write
Enable causes the clock edge to write the data
input signal to the memory location pointed to
by the address inputs. Active High by default
with built-in programmable polarity.
A0, A1, A2, A3
(A4, A5)
The address inputs select the memory cells for
read or write. The width of the port determines
the required address inputs.
D The data input provides the new data value to
be written into the RAM.
O, SPO, and
DPO
The data output O on single-port RAM or the
SPO and DPO outputs on dual-port RAM
reflects the contents of the memory cells
referenced by the address inputs. Following an
active write clock edge, the data out (O or
SPO) reflects the newly written data.
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Product Specification 34
initialized distributed RAM contents are not disturbed during
the configuration process.
The distributed RAM is useful for smaller amounts of
memory. Larger memory requirements can use the
dedicated 18Kbit RAM blocks (see Block RAM).
Shift Registers
For additional information, refer to the “Using Look-Up
Tables as Shift Registers (SRL16)” chapter in UG331.
It is possible to program each SLICEM LUT as a 16-bit shift
register (see Figure 28). Used in this way, each LUT can
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting
programmable delays can be used to balance the timing of
data pipelines.
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see Figure 15). SHIFTIN and
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the
addressable bit.
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 29 for an example of the SRLC16E component.
The functionality of the shift register is shown in Table 20.
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
X-Ref Target - Figure 28
Figure 28: Logic Cell SRL16 Structure
A[3:0]
SHIFTIN
SHIFTOUT
or YB
DI (BY)
D
MC15
DI
WSG
CE (SR)
CLK
SRLC16
DQ
SHIFT-REG
WE
CK
A[3:0] Output
Registered
Output
(optional)
4
X465_03_040203
WS
X-Ref Target - Figure 29
Figure 29: SRL16 Shift Register Component with
Cascade and Clock Enable
Table 20: SRL16 Shift Register Function
Inputs Outputs
Am CLK CE D Q Q15
Am X0X Q[Am] Q[15]
Am 1 D Q[Am-1] Q[15]
Notes:
1. m = 0, 1, 2, 3.
SRLC16E
DQ
CE
CLK
A0
A1
A2
A3
Q15
DS312-2_43_021305
Spartan-3E FPGA Family: Functional Description
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Product Specification 35
Block RAM
For additional information, refer to the “Using Block RAM”
chapter in UG331.
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM
synchronously stores large amounts of data while
distributed RAM, previously described, is better suited for
buffering small amounts of data anywhere along signal
paths. This section describes basic block RAM functions.
Each block RAM is configurable by setting the content’s
initial values, default signal value of the output registers,
port aspect ratios, and write modes. Block RAM can be
used in single-port or dual-port modes.
Arrangement of RAM Blocks on Die
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The
Spartan-3E devices ranging from the XC3S250E to
XC3S1600E have two columns of block RAM. Table 21
shows the number of RAM blocks, the data storage
capacity, and the number of columns for each device.
Row(s) of CLBs are located above and below each block
RAM column.
Immediately adjacent to each block RAM is an embedded
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16
bits of the A multiplicand input bus of the multiplier. Similarly,
the upper 16 bits of Port B's data input bus are shared with
the B multiplicand input bus of the multiplier.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common block RAM, which has a maximum capacity of
18,432 bits, or 16,384 bits with no parity bits (see parity bits
description in Table 22). Each port has its own dedicated
set of data, control, and clock lines for synchronous read
and write operations. There are four basic data paths, as
shown in Figure 30:
1. Write to and read from Port A
2. Write to and read from Port B
3. Data transfer from Port A to Port B
4. Data transfer from Port B to Port A
Number of Ports
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[wA]_S[wB] calls out the dual-port
primitive, where the integers wA and wB specify the total
data path width at ports A and B, respectively. Thus, a
RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
RAMB16_S18 is a single-port RAM with an 18-bit port.
Port Aspect Ratios
Each port of the block RAM can be configured
independently to select a number of different possible
widths for the data input (DI) and data output (DO) signals
as shown in Table 22.
Table 21: Number of RAM Blocks by Device
Device
Total
Number of
RAM Blocks
Total
Addressable
Locations
(bits)
Number of
Columns
XC3S100E 4 73,728 1
XC3S250E 12 221,184 2
XC3S500E 20 368,640 2
XC3S1200E 28 516,096 2
XC3S1600E 36 663,552 2
X-Ref Target - Figure 30
Figure 30: Block RAM Data Paths
DS312-2_01_020705
Spartan-3E
Dual-Port
Block RAM
Read 3
Read
Write
Write
Read
Write
Write
Read
Port A
Port B
2
1
4
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Product Specification 36
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in Figure 31. When data is written to a port
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words.
Parity bits are not available if the data port width is
configured as x4, x2, or x1. For example, if a x36 data word
(32 data, 4 parity) is addressed as two x18 halfwords (16
data, 2 parity), the parity bits associated with each data byte
are mapped within the block RAM to the appropriate parity
bits. The same effect happens when the x36 data word is
mapped as four x9 words.
Table 22: Port Aspect Ratios
Total Data
Path Width
(w bits)
DI/DO Data
Bus Width
(w-p bits)(1)
DIP/DOP
Parity Bus
Width (p bits)
ADDR
Bus Width
(r bits)(2)
DI/DO
[w-p-1:0]
DIP/DOP
[p-1:0]
ADDR
[r-1:0]
No. of
Addressable
Locations (n)(3)
Block RAM
Capacity
(w*n bits)(4)
1 1 0 14 [0:0] - [13:0] 16,384 16,384
2 2 0 13 [1:0] - [12:0] 8,192 16,384
4 4 0 12 [3:0] - [11:0] 4,096 16,384
9 8 1 11 [7:0] [0:0] [10:0] 2,048 18,432
18 16 2 10 [15:0] [1:0] [9:0] 1,024 18,432
36 32 4 9 [31:0] [3:0] [8:0] 512 18,432
Notes:
1. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
2. The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log9(2)].
3. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2r.
4. The product of w and n yields the total block RAM capacity.
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Product Specification 37
X-Ref Target - Figure 31
Figure 31: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
Byte 0Byte 1Byte 2Byte 3
Byte 0Byte 1
Byte 2Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
0123
4567
Byte 3
0
0
1
0
1
2
3
0
1
6
7
01
23
45
67
Byte
0
01
23
45
67
Byte 3
0
1
2
3
P0
P2
P0P1P2P3
P2P3
P0P1
P3
P1
0
1
2
3
Byte 0
4
5
6
7
Byte 3
0
1
2
3
C
D
E
F
1C
1D
1E
1F
1617 815
08162432333435 31 23 15 7
07
078
23
0123
4567
yte 0
01
01
0
Address
512x36
1Kx18
2Kx9
4Kx4
8Kx2
16Kx1
Parity Data
B
DS312-2_02_102105
No Parity
(16Kbits data)
Parity Optional
(16Kbits data,
2Kbits parity)
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Product Specification 38
Block RAM Port Signal Definitions
Representations of the dual-port primitive
RAMB16_S[wA]_S[wB] and the single-port primitive
RAMB16_S[w] with their associated signals are shown in
Figure 32a and Figure 32b, respectively. These signals are
defined in Table 23. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
Design Note
Whenever a block RAM port is enabled (ENA or
ENB = High), all address transitions must meet the data
sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in Table 103, page 139.This
requirement must be met even if the RAM read output is of
no interest.
X-Ref Target - Figure 32
Figure 32: Block RAM Primitives
DS312-2_03_111105
WEA
ENA
SSRA
CLKA
ADDRA[rA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
DOPA[pA–1:0]
DOA[wA–pA–1:0]
RAMB16_SWA_SWB
(a) Dual-Port (b) Single-Port
DOPB[pB–1:0]
DOB[wB–pB–1:0]
WEB
ENB
SSRB
CLKB
ADDRB[rB–1:0]
DIB[wBpB–1:0]
DIPB[pB–1:0]
WE
EN
SSR
CLK
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
DOP[p–1:0]
DO[w–p–1:0]
RAMB16_Sw
Notes:
1. wA and wB are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
2. pA and pB are integers that indicate the number of data path lines serving as parity bits.
3. rA and rB are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
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Product Specification 39
Table 23: Block RAM Port Signals
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Direction Function
Address Bus ADDRA ADDRB Input The Address Bus selects a memory location for read or write operations.
The width (w) of the port’s associated data path determines the number of
available address lines (r), as per Table 22.
Whenever a port is enabled (ENA or ENB = High), address transitions must
meet the data sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in Table 103, page 139.This requirement must
be met even if the RAM read output is of no interest.
Data Input Bus DIA DIB Input Data at the DI input bus is written to the RAM location specified by the
address input bus (ADDR) during the active edge of the CLK input, when
the clock enable (EN) and write enable (WE) inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based on
Table 22. This selection applies to both the DI and DO paths of a given port.
Parity Data Input(s) DIPA DIPB Input Parity inputs represent additional bits included in the data input path.
Although referred to herein as “parity” bits, the parity inputs and outputs
have no special functionality for generating or checking parity and can be
used as additional data bits. The number of parity bits ‘p’ included in the DI
(same as for the DO bus) depends on a port’s total data path width (w). See
Table 22.
Data Output Bus DOA DOB Output Data is written to the DO output bus from the RAM location specified by the
address input bus, ADDR. See the DI signal description for DO port width
configurations.
Basic data access occurs on the active edge of the CLK when WE is
inactive and EN is active. The DO outputs mirror the data stored in the
address ADDR memory location. Data access with WE active if the
WRITE_MODE attribute is set to the value: WRITE_FIRST, which
accesses data after the write takes place. READ_FIRST accesses data
before the write occurs. A third attribute, NO_CHANGE, latches the DO
outputs upon the assertion of WE. See Block RAM Data Operations for
details on the WRITE_MODE attribute.
Parity Data
Output(s)
DOPA DOPB Output Parity outputs represent additional bits included in the data input path. The
number of parity bits ‘p’ included in the DI bus (same as for the DO bus)
depends on a port’s total data path width (w). See the DIP signal
description for configuration details.
Write Enable WEA WEB Input When asserted together with EN, this input enables the writing of data to
the RAM. When WE is inactive with EN asserted, read operations are still
possible. In this case, a latch passes data from the addressed memory
location to the DO outputs.
Clock Enable ENA ENB Input When asserted, this input enables the CLK signal to perform read and write
operations to the block RAM. When inactive, the block RAM does not
perform any read or write operations.
Set/Reset SSRA SSRB Input When asserted, this pin forces the DO output latch to the value of the
SRVAL attribute. It is synchronized to the CLK signal.
Clock CLKA CLKB Input This input accepts the clock signal to which read and write operations are
synchronized. All associated port inputs are required to meet setup times
with respect to the clock signal’s active edge. The data output bus responds
after a clock-to-out delay referenced to the clock signal’s active edge.
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Product Specification 40
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 24.
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 25 describes the data
operations of each port as a result of the block RAM control
signals in their default active-High edges.
The waveforms for the write operation are shown in the top
half of Figure 33, Figure 34, and Figure 35. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Table 24: Block RAM Attributes
Function Attribute Possible Values
Initial Content for Data Memory, Loaded during
Configuration
INITxx
(INIT_00 through INIT3F)
Each initialization string defines 32 hex values of the
16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
during Configuration
INITPxx
(INITP_00 through INITP0F)
Each initialization string defines 32 hex values of the
2048-bit parity data memory of the block RAM.
Data Output Latch Initialization INIT (single-port)
INITA, INITB (dual-port)
Hex value the width of the chosen port.
Data Output Latch Synchronous Set/Reset
Value
SRVAL (single-port)
SRVAL_A, SRVAL_B (dual-port)
Hex value the width of the chosen port.
Data Output Latch Behavior during Write (see
Block RAM Data Operations)
WRITE_MODE WRITE_FIRST, READ_FIRST, NO_CHANGE
Table 25: Block RAM Function Table
Input Signals Output Signals RAM Data
GSR EN SSR WE CLK ADDR DIP DI DOP DO Parity Data
Immediately After Configuration
Loaded During Configuration X X INITP_xx INIT_xx
Global Set/Reset Immediately After Configuration
1 X X X X X X X INIT INIT No Chg No Chg
RAM Disabled
0 0 X X X X X X No Chg No Chg No Chg No Chg
Synchronous Set/Reset
0110X X X SRVAL SRVAL No Chg No Chg
Synchronous Set/Reset During Write RAM
0111addr pdata Data SRVAL SRVAL RAM(addr)
pdata
RAM(addr)
data
Read RAM, no Write Operation
0100addr X X RAM(pdata) RAM(data) No Chg No Chg
Write RAM, Simultaneous Read Operation
0101addr pdata Data WRITE_MODE = WRITE_FIRST
pdata data RAM(addr)
pdata
RAM(addr)
data
WRITE_MODE = READ_FIRST
RAM(data) RAM(data) RAM(addr)
pdata
RAM(addr)
pdata
WRITE_MODE = NO_CHANGE
No Chg No Chg RAM(addr)
pdata
RAM(addr)
pdata
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Product Specification 41
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
portions of Figure 33, Figure 34, and Figure 35 during
which WE is Low.
Data also can be accessed on the DO outputs when
asserting the WE input based on the value of the
WRITE_MODE attribute as described in Table 26.
Setting the WRITE_MODE attribute to a value of
WRITE_FIRST, data is written to the addressed memory
location on an enabled active CLK edge and is also passed
to the DO outputs. WRITE_FIRST timing is shown in the
portion of Figure 33 during which WE is High.
Setting the WRITE_MODE attribute to a value of
READ_FIRST, data already stored in the addressed
location passes to the DO outputs before that location is
overwritten with new data from the DI inputs on an enabled
active CLK edge. READ_FIRST timing is shown in the
portion of Figure 34 during which WE is High.
Table 26: WRITE_MODE Effect on Data Output Latches During Write Operations
Write Mode Effect on Same Port Effect on Opposite Port
(dual-port only with same address)
WRITE_FIRST
Read After Write
Data on DI and DIP inputs is written into specified
RAM location and simultaneously appears on DO and
DOP outputs.
Invalidates data on DO and DOP outputs.
READ_FIRST
Read Before Write
Data from specified RAM location appears on DO and
DOP outputs.
Data on DI and DIP inputs is written into specified
location.
Data from specified RAM location appears on DO and
DOP outputs.
NO_CHANGE
No Read on Write
Data on DO and DOP outputs remains unchanged.
Data on DI and DIP inputs is written into specified
location.
Invalidates data on DO and DOP outputs.
X-Ref Target - Figure 33
Figure 33: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
CLK
WE
DI
ADDR
DO
EN
DISABLED READ
XXXX 1111 2222 XXXX
aa bb cc dd
0000 MEM(aa) 1111 2222 MEM(dd)
READWRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
DS312-2_05_020905
Data_in Internal
Memory DO Data_out = Data_in
DI
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Product Specification 42
Setting the WRITE_MODE attribute to a value of
NO_CHANGE, puts the DO outputs in a latched state when
asserting WE. Under this condition, the DO outputs retain
the data driven just before WE is asserted. NO_CHANGE
timing is shown in the portion of Figure 35 during which WE
is High.
X-Ref Target - Figure 34
Figure 34: Waveforms of Block RAM Data Operations with READ_FIRST Selected
X-Ref Target - Figure 35
Figure 35: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
CLK
WE
DI
ADDR
DO
EN
DISABLED READ
XXXX 1111 2222 XXXX
aa bb cc dd
0000 MEM(aa) old MEM(bb) old MEM(cc) MEM(dd)
READWRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
DS312-2_06_020905
Data_in Internal
Memory DO Prior stored data
DI
CLK
WE
DI
ADDR
DO
EN
DISABLED READ
XXXX 1111 2222 XXXX
aa bb cc dd
0000 MEM(aa) MEM(dd)
READWRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
DS312-2_07_020905
Data_in Internal
Memory DO No change during write
DI
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Product Specification 43
Dedicated Multipliers
For additional information, refer to the “Using Embedded
Multipliers” chapter in UG331.
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See Arrangement of RAM Blocks on Die for details
on the location of these blocks and their connectivity.
Operation
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications, such as simple data storage and
barrel shifting. Logic slices also implement efficient small
multipliers and thereby supplement the dedicated
multipliers. The Spartan-3E dedicated multiplier blocks
have additional features beyond those provided in
Spartan-3 FPGAs.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values
ranging from –131,07210 to +131,07110 with a resulting
product ranging from –17,179,738,11210 to
+17,179,869,18410.
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the
most-significant bit). Wider multiplication operations are
performed by combining the dedicated multipliers and
slice-based logic in any viable combination or by
time-sharing a single multiplier. Perform unsigned
multiplication by restricting the inputs to the positive range.
Tie the most-significant bit Low and represent the unsigned
value in the remaining 17 lesser-significant bits.
Optional Pipeline Registers
As shown in Figure 36, each multiplier block has optional
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an
independent clock enable and synchronous reset controls
making them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Figure 36 illustrates the principle features of the multiplier
block.
Use the MULT18X18SIO primitive shown in Figure 37 to
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a
multiplier, adding the pipeline registers might require the
MULT18X18SIO primitive. Connect the appropriate signals
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the
associated register, or to 0 to remove it and make the signal
path combinatorial.
X-Ref Target - Figure 36
Figure 36: Principle Ports and Functions of Dedicated Multiplier Blocks
X
CECEA
AREG
(Optional)
BREG
(Optional)
RSTA
A[17:0]
P[35:0]
DQ
RST
CECEP
PREG
(Optional)
RSTP
DQ
RST
CECEB
RSTB
B[17:0]
CLK
DQ
RST
DS312-2_27_021205
Spartan-3E FPGA Family: Functional Description
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Product Specification 44
Cascading Multipliers
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the
multiplier’s ‘B’ input among several multiplier bocks. The
18-bit BCIN “cascade” input port offers an alternate input
source from the more typical ‘B’ input. The B_INPUT
attribute specifies whether the specific implementation uses
the BCIN or ‘B’ input path. Setting B_INPUT to DIRECT
chooses the ‘B’ input. Setting B_INPUT to CASCADE
selects the alternate BCIN input. The BREG register then
optionally holds the selected input value, if required.
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
Figure 38 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
X-Ref Target - Figure 37
Figure 37: MULT18X18SIO Primitive
MULT18X18SIO
A[17:0] P[35:0]
BCOUT[17:0]
B[17:0]
CEA
CEB
CEP
CLK
RSTA
RSTB
RSTP
BCIN[17:0]
DS312-2_28_021205
X-Ref Target - Figure 38
Figure 38: Four Configurations of the B Input
X
CECEB
RSTB
BCIN[17:0] BCIN[17:0]
CLK
DQ
RST
BCOUT[17:0]
BREG = 1
B_INPUT = CASCADE
BREG = 0
B_INPUT = CASCADE
X
CECEB
RSTB
B[17:0]
BREG
BREG
CLK
DQ
RST
BCOUT[17:0]
BREG = 1
B_INPUT = DIRECT
X
BCOUT[17:0]
B[17:0]
BREG = 0
B_INPUT = DIRECT
X
BCOUT[17:0]
DS312-2_29_021505
Spartan-3E FPGA Family: Functional Description
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Product Specification 45
The BCIN and BCOUT ports have associated dedicated
routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of
one multiplier block drives the BCIN port of the multiplier
block directly above it. There is no connection to the BCIN
port of the bottom-most multiplier block in a column or a
connection from the BCOUT port of the top-most block in a
column. As an example, Figure 39 shows the multiplier
cascade capability within the XC3S100E FPGA, which has
a single column of multiplier, four blocks tall. For clarity, the
figure omits the register control inputs.
When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP
algorithms such as direct-form FIR filters. When the BREG
register is omitted, the cascade structure essentially feeds
the same input value to more than one multiplier. This
parallel connection serves to create wide-input multipliers,
implement transpose FIR filters, and is used in any
application that requires that several multipliers have the
same input value.
X-Ref Target - Figure 39
Figure 39: Multiplier Cascade Connection
BCOUT
BCINB_INPUT = CASCADE
A
P
B
A
B
A
B
A
B
DS312-2_30_021505
BCOUT
BCINB_INPUT = CASCADE
P
BCOUT
BCINB_INPUT = CASCADE
P
BCOUT
BCINB_INPUT = DIRECT
P
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Product Specification 46
Multiplier/Block RAM Interaction
Each multiplier is located adjacent to an 18 Kbit block RAM
and shares some interconnect resources. Configuring an
18 Kbit block RAM for 36-bit wide data (512 x 36 mode)
prevents use of the associated dedicated multiplier.
The upper 16 bits of the ‘A’ multiplicand input are shared
with the upper 16 bits of the block RAM’s Port A Data input.
Similarly, the upper 16 bits of the ‘B’ multiplicand input are
shared with Port B’s data input. See also Figure 48,
page 63.
Table 27 defines each port of the MULT18X18SIO primitive.
Table 27: MULT18X18SIO Embedded Multiplier Primitives Description
Signal Name Direction Function
A[17:0] Input The primary 18-bit two’s complement value for multiplication. The block multiplies by this value
asynchronously if the optional AREG and PREG registers are omitted. When AREG and/or
PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject
to the appropriate register controls.
B[17:0] Input The second 18-bit two’s complement value for multiplication if the B_INPUT attribute is set to
DIRECT. The block multiplies by this value asynchronously if the optional BREG and PREG
registers are omitted. When BREG and/or PREG are used, the value provided on this port is
qualified by the rising edge of CLK, subject to the appropriate register controls.
BCIN[17:0] Input The second 18-bit two’s complement value for multiplication if the B_INPUT attribute is set to
CASCADE. The block multiplies by this value asynchronously if the optional BREG and PREG
registers are omitted. When BREG and/or PREG are used, the value provided on this port is
qualified by the rising edge of CLK, subject to the appropriate register controls.
P[35:0] Output The 36-bit two’s complement product resulting from the multiplication of the two input values
applied to the multiplier. If the optional AREG, BREG and PREG registers are omitted, the
output operates asynchronously. Use of PREG causes this output to respond to the rising edge
of CLK with the value qualified by CEP and RSTP. If PREG is omitted, but AREG and BREG
are used, this output responds to the rising edge of CLK with the value qualified by CEA, RSTA,
CEB, and RSTB. If PREG is omitted and only one of AREG or BREG is used, this output
responds to both asynchronous and synchronous events.
BCOUT[17:0] Output The value being applied to the second input of the multiplier. When the optional BREG register
is omitted, this output responds asynchronously in response to changes at the B[17:0] or
BCIN[17:0] ports according to the setting of the B_INPUT attribute. If BREG is used, this output
responds to the rising edge of CLK with the value qualified by CEB and RSTB.
CEA Input Clock enable qualifier for the optional AREG register. The value provided on the A[17:0] port is
captured by AREG in response to a rising edge of CLK when this signal is High, provided that
RSTA is Low.
RSTA Input Synchronous reset for the optional AREG register. AREG content is forced to the value zero in
response to a rising edge of CLK when this signal is High.
CEB Input Clock enable qualifier for the optional BREG register. The value provided on the B[17:0] or
BCIN[17:0] port is captured by BREG in response to a rising edge of CLK when this signal is
High, provided that RSTB is Low.
RSTB Input Synchronous reset for the optional BREG register. BREG content is forced to the value zero in
response to a rising edge of CLK when this signal is High.
CEP Input Clock enable qualifier for the optional PREG register. The value provided on the output of the
multiplier port is captured by PREG in response to a rising edge of CLK when this signal is High,
provided that RSTP is Low.
RSTP Input Synchronous reset for the optional PREG register. PREG content is forced to the value zero in
response to a rising edge of CLK when this signal is High.
Notes:
1. The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity.
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Product Specification 47
Digital Clock Managers (DCMs)
For additional information, refer to the “Using Digital Clock
Managers (DCMs)” chapter in UG331.
Differences from the Spartan-3 Architecture
Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
The variable phase shifting feature functions differently
on Spartan-3E FPGAs than from Spartan-3 FPGAs.
The Spartan-3E DLLs support lower input frequencies,
down to 5 MHz. Spartan-3 DLLs support down to
18 MHz.
Overview
Spartan-3E FPGA Digital Clock Managers (DCMs) provide
flexible, complete control over clock frequency, phase shift
and skew. To accomplish this, the DCM employs a
Delay-Locked Loop (DLL), a fully digital control system that
uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in
operating temperature and voltage. This section provides a
fundamental description of the DCM.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also Figure 45). The DCM in Spartan-3E FPGAs is
surrounded by CLBs within the logic array and is no longer
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture. The Digital Clock Manager is
instantiated within a design using a “DCM” primitive.
The DCM supports three major functions:
Clock-skew Elimination: Clock skew within a system
occurs due to the different arrival times of a clock signal
at different points on the die, typically caused by the
clock signal distribution network. Clock skew increases
setup and hold time requirements and increases
clock-to-out times, all of which are undesirable in high
frequency applications. The DCM eliminates clock
skew by phase-aligning the output clock signal that it
generates with the incoming clock signal. This
mechanism effectively cancels out the clock distribution
delays.
Frequency Synthesis: The DCM can generate a wide
range of different output clock frequencies derived from
the incoming clock signal. This is accomplished by
either multiplying and/or dividing the frequency of the
input clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
the input clock signal.
Although a single design primitive, the DCM consists of four
interrelated functional units: the Delay-Locked Loop (DLL),
the Digital Frequency Synthesizer (DFS), the Phase Shifter
(PS), and the Status Logic. Each component has its
associated signals, as shown in Figure 40.
X-Ref Target - Figure 40
Figure 40: DCM Functional Blocks and Associated Signals
DS099-2_07_101205
PSINCDEC
PSEN
PSCLK
CLKIN
CLKFB
RST
STAT U S [7:0]
LOCKED
8
CLKFX180
CLKFX
CLK0
PSDONE
Clock
Distribution
Delay
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Status
Logic
DFS
DLL
Phase
Shifter
Delay Steps
Output Stage
Input Stage
DCM
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Product Specification 48
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to
eliminate clock skew. The main signal path of the DLL
consists of an input stage, followed by a series of discrete
delay elements or steps, which in turn leads to an output
stage. This path together with logic for phase detection and
control forms a system complete with feedback as shown in
Figure 41. In Spartan-3E FPGAs, the DLL is implemented
using a counter-based delay line.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 28. The clock outputs drive
simultaneously. Signals that initialize and report the state of
the DLL are discussed in Status Logic.
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network that feeds all
the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the
clock distribution network, the clock signal returns to the
DLL via a feedback line called CLKFB. The control block
inside the DLL measures the phase error between CLKFB
and CLKIN. This phase error is a measure of the clock skew
that the clock distribution network introduces. The control
block activates the appropriate number of delay steps to
X-Ref Target - Figure 41
Figure 41: Simplified Functional Diagram of DLL
Table 28: DLL Signals
Signal Direction Description
CLKIN Input Receives the incoming clock signal. See Table 30, Table 31, and Table 32 for optimal external
inputs to a DCM.
CLKFB Input Accepts either CLK0 or CLK2X as the feedback signal. (Set the CLK_FEEDBACK attribute
accordingly).
CLK0 Output Generates a clock signal with the same frequency and phase as CLKIN.
CLK90 Output Generates a clock signal with the same frequency as CLKIN, phase-shifted by 90°.
CLK180 Output Generates a clock signal with the same frequency as CLKIN, phase-shifted by 180°.
CLK270 Output Generates a clock signal with the same frequency as CLKIN, phase-shifted by 270°.
CLK2X Output Generates a clock signal with the same phase as CLKIN, and twice the frequency.
CLK2X180 Output Generates a clock signal with twice the frequency of CLKIN, and phase-shifted 180° with respect
to CLK2X.
CLKDV Output Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal
that is phase-aligned to CLKIN.
DS099-2_08_041103
CLKIN Delay
n
CLKFB
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Output Section
Control
Delay
n-1
Phase
Detection
LOCKED
Delay
2
Delay
1
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Product Specification 49
cancel out the clock skew. When the DLL phase-aligns the
CLK0 signal with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
DLL Attributes and Related Functions
The DLL unit has a variety of associated attributes as
described in Table 29. Each attribute is described in detail in
the sections that follow.
DLL Clock Input Connections
For best results, an external clock source enters the FPGA
via a Global Clock Input (GCLK). Each specific DCM has
four possible direct, optimal GCLK inputs that feed the
DCM’s CLKIN input, as shown in Table 30. Table 30 also
provides the specific pin numbers by package for each
GCLK input. The two additional DCM’s on the XC3S1200E
and XC3S1600E have similar optimal connections from the
left-edge LHCLK and the right-edge RHCLK inputs, as
described in Table 31 and Table 32.
The DCM supports differential clock inputs (for
example, LVDS, LVPECL_25) via a pair of GCLK inputs
that feed an internal single-ended signal to the DCM’s
CLKIN input.
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
Table 29: DLL Attributes
Attribute Description Values
CLK_FEEDBACK Chooses either the CLK0 or CLK2X output to drive
the CLKFB input
NONE, 1X, 2X
CLKIN_DIVIDE_BY_2 Halves the frequency of the CLKIN signal just as it
enters the DCM
FALSE, TRUE
CLKDV_DIVIDE Selects the constant used to divide the CLKIN input
frequency to generate the CLKDV output frequency
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0,
7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16
CLKIN_PERIOD Additional information that allows the DLL to
operate with the most efficient lock time and the
best jitter tolerance
Floating-point value representing the
CLKIN period in nanoseconds
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Product Specification 50
Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs
Package
Differential Pair Differential Pair Differential Pair Differential Pair
NPNP NPNP
Pin Number for Single-Ended Input Pin Number for Single-Ended Input
VQ100 P91 P90 P89 P88 P86 P85 P84 P83
CP132 B7 A7 C8 B8 A9 B9 C9 A10
TQ144 P131 P130 P129 P128 P126 P125 P123 P122
PQ208 P186 P185 P184 P183 P181 P180 P178 P177
FT256 D8 C8 B8 A8 A9 A10 F9 E9
FG320 D9 C9 B9 B8 A10 B10 E10 D10
FG400 A9 A10 G10 H10 E10 E11 G11 F11
FG484 B11 C11 H11 H12 C12 B12 E12 F12
Associated Global Buffers 
GCLK11 GCLK10 GCLK9 GCLK8
BUFGMUX_X1Y10
BUFGMUX_X1Y11
BUFGMUX_X2Y10
BUFGMUX_X2Y11
GCLK7 GCLK6 GCLK5 GCLK4
Top Left DCM
XC3S100: N/A
XC3S250E, XC3S500E: DCM_X0Y1
XC3S1200E, XC3S1600E: DCM_X1Y3
Top Right DCM
XC3S100: DCM_X0Y1
XC3S250E, XC3S500E: DCM_X1Y1
XC3S1200E, XC3S1600E: DCM_X2Y3

H G F E
Clock Line (see Table 41)
D C B A

Bottom Left DCM
XC3S100: N/A
XC3S250E, XC3S500E: DCM_X0Y0
XC3S1200E, XC3S1600E: DCM_X1Y0
BUFGMUX_X1Y0
BUFGMUX_X1Y1
BUFGMUX_X2Y0
BUFGMUX_X2Y1
Bottom Right DCM
XC3S100: DCM_X0Y0
XC3S250E, XC3S500E: DCM_X1Y0
XC3S1200E, XC3S1600E: DCM_X2Y0
GCLK12 GCLK13 GCLK14 GCLK15 GCLK0 GCLK1 GCLK2 GCLK3
Associated Global Buffers 
Package
Differential Pair Differential Pair Differential Pair Differential Pair
PNPN PNPN
Pin Number for Single-Ended Input Pin Number for Single-Ended Input
VQ100 P32 P33 P35 P36 P38 P39 P40 P41
CP132 M4 N4 M5 N5 M6 N6 P6 P7
TQ144 P50 P51 P53 P54 P56 P57 P58 P59
PQ208 P74 P75 P77 P78 P80 P81 P82 P83
FT256 M8 L8 N8 P8 T9 R9 P9 N9
FG320 N9 M9 U9 V9 U10 T10 R10 P10
FG400 W9 W10 R10 P10 P11 P12 V10 V11
FG484 V11 U11 R11 T11 R12 P12 Y12 W12
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Product Specification 51
Every FPGA input provides a possible DCM clock input, but
the path is not temperature and voltage compensated like
the GCLKs. Alternatively, clock signals within the FPGA
optionally provide a DCM clock input via a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and
external connections are shown in Figure 42a and
Figure 42c, respectively.
Table 31: Direct Clock Input and Optional External Feedback to Left-Edge DCMs (XC3S1200E and XC3S1600E)
Diff.
Clock
Single-Ended Pin Number by Package Type Left Edge
VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 LHCLK DCM/BUFGMUX
BUFGMUX_X0Y5 D
BUFGMUX_X0Y4 C
Pair
PP9 F3 P14 P22 H5 J5 K3 M5 LHCLK0
DCM_X0Y2
Clock Lines
NP10F2P15P23H6 J4 K2 L5LHCLK1
Pair
PP11F1P16P24H3 J1 K7 L8LHCLK2
NP12G1P17P25H4 J2 L7 M8LHCLK3
BUFGMUX_X0Y3 B
BUFGMUX_X0Y2 A
BUFGMUX_X0Y9 H
BUFGMUX_X0Y8 G
Pair
PP15G3P20P28 J2 K3 M1 M1LHCLK4
DCM_X0Y1
Clock Lines
NP16H1P21P29J3 K4 L1 N1LHCLK5
Pair
PP17H2P22P30J5 K6 M3 M3LHCLK6
NP18H3P23P31J4 K5 L3 M4LHCLK7
BUFGMUX_X0Y7 F
BUFGMUX_X0Y6 E
Table 32: Direct Clock Input and Optional External Feedback to Right-Edge DCMs (XC3S1200E and XC3S1600E)
Right Edge Single-Ended Pin Number by Package Type Diff.
Clock
DCM/BUFGMUX RHCLK VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
DBUFGMUX_X3Y5
CBUFGMUX_X3Y4
Clock Lines
DCM_X3Y2
RHCLK7 P68 G13 P94 P135 H11 J14 J20 L19 N
Pair
RHCLK6 P67 G14 P93 P134 H12 J15 K20 L18 P
RHCLK5 P66 H12 P92 P133 H14 J16 K14 L21 N
Pair
RHCLK4 P65 H13 P91 P132 H15 J17 K13 L20 P
BBUFGMUX_X3Y3
ABUFGMUX_X3Y2
HBUFGMUX_X3Y9
GBUFGMUX_X3Y8
Clock Lines
DCM_X3Y1
RHCLK3 P63 J14 P88 P129 J13 K14 L14 M16 N
Pair
RHCLK2 P62 J13 P87 P128 J14 K15 L15 M15 P
RHCLK1 P61 J12 P86 P127 J16 K12 L16 M22 N
Pair
RHCLK0 P60 K14 P85 P126 K16 K13 M16 N22 P
FBUFGMUX_X3Y7
EBUFGMUX_X3Y6
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 52
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can
simultaneously drive four of the BUFGMUX buffers on the
same die edge. All DCM clock outputs can simultaneously
drive general routing resources, including interconnect
leading to OBUF buffers.
The feedback loop is essential for DLL operation. Either the
CLK0 or CLK2X outputs feed back to the CLKFB input via a
BUFGMUX global buffer to eliminate the clock distribution
delay. The specific BUFGMUX buffer used to feed back the
CLK0 or CLK2X signal is ideally one of the BUFGMUX
buffers associated with a specific DCM, as shown in
Table 30, Table 31, and Table 32.
The feedback path also phase-aligns the other seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The CLK_FEEDBACK attribute value must
agree with the physical feedback connection. Use “1X” for
CLK0 feedback and “2X” for CLK2X feedback. If the DFS
unit is used stand-alone, without the DLL, then no feedback
is required and set the CLK_FEEDBACK attribute to
“NONE”.
Two basic cases determine how to connect the DLL clock
outputs and feedback connections: on-chip synchronization
and off-chip synchronization, which are illustrated in
Figure 42a through Figure 42d.
In the on-chip synchronization case in Figure 42a and
Figure 42b, it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 42a, the feedback loop is
created by routing CLK0 (or CLK2X) in Figure 42b to a
global clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case in Figure 42c and
Figure 42d, CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 42c, the feedback loop is
formed by feeding CLK0 (or CLK2X) in Figure 42d back into
the FPGA, then to the DCM’s CLKFB input via a Global
Buffer Input, specified in Table 30.
X-Ref Target - Figure 42
Figure 42: Input Clock, Output Clock, and Feedback Connections for the DLL
DS099-2_09_082104
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLK0
CLK0
Clock
Net Delay
BUFGMUX
BUFGMUX
BUFG
FPGA
(a) On-Chip with CLK0 Feedback
CLKIN
DCM
CLKFB
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLK0
CLK0
Clock
Net Delay
IBUFG
IBUFG
FPGA
(c) Off-Chip with CLK0 Feedback
CLKIN
DCM
CLKFB
OBUF
OBUF
CLK2X
CLK2X
IBUFG
IBUFG
FPGA
(d) Off-Chip with CLK2X Feedback
CLKIN
DCM
CLKFB
OBUF
OBUF
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X180
CLK2X
CLK2X
Clock
Net Delay
Clock
Net Delay
BUFGMUX
BUFGMUX
BUFG
FPGA
(b) On-Chip with CLK2X Feedback
CLKIN
DCM
CLKFB
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X180
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 53
Accommodating Input Frequencies Beyond Spec-
ified Maximums
If the CLKIN input frequency exceeds the maximum
permitted, divide it down to an acceptable value using the
CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to
“TRUE”, the CLKIN frequency is divided by a factor of two
as it enters the DCM. In addition, the CLKIN_DIVIDE_BY_2
option produces a 50% duty-cycle on the input clock,
although at half the CLKIN frequency.
Quadrant and Half-Period Phase Shift Outputs
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted
signals, respectively. These signals are described in
Table 28, page 48 and their relative timing is shown in
Figure 43. For control in finer increments than 90°, see
Phase Shifter (PS).
Basic Frequency Synthesis Outputs
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also
doubles the frequency, but is 180° out-of-phase with respect
to CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to
various values as described in Table 29. The basic
frequency synthesis outputs are described in Table 28.
Duty Cycle Correction of DLL Clock Outputs
The DLL output signals exhibit a 50% duty cycle, even if the
incoming CLKIN signal has a different duty cycle.
Fifty-percent duty cycle means that the High and Low times
of each clock cycle are equal.
DLL Performance Differences Between Steppings
As indicated in Digital Clock Manager (DCM) Timing
(Module 3), the Stepping 1 revision silicon supports higher
maximum input and output frequencies. Stepping 1 devices
are backwards compatible with Stepping 0 devices.
Digital Frequency Synthesizer (DFS)
The DFS unit generates clock signals where the output
frequency is a product of the CLKIN input clock frequency
and a ratio of two user-specified integers. The two
dedicated outputs from the DFS unit, CLKFX and
CLKFX180, are defined in Table 33.
The signal at the CLKFX180 output is essentially an
inversion of the CLKFX signal. These two outputs always
exhibit a 50% duty cycle, even when the CLKIN signal does
not. The DFS clock outputs are active coincident with the
seven DLL outputs and their output phase is controlled by
the Phase Shifter unit (PS).
The output frequency (fCLKFX) of the DFS is a function of the
incoming clock frequency (fCLKIN) and two integer
attributes, as follows.
Eq 1
The CLKFX_MULTIPLY attribute is an integer ranging from
2 to 32, inclusive, and forms the numerator in Equation 1.
X-Ref Target - Figure 43
Figure 43: Characteristics of the DLL Clock Outputs
Output Signal - Duty Cycle Corrected
Phase:
Input Signal (40%/60% Duty Cycle)
0o90o180o270o0o90o180o270o0o
DS099-2_10_101105
CLKIN
t
CLK2X
CLK2X180
CLKDV
CLK0
CLK90
CLK180
CLK270
Table 33: DFS Signals
Signal Direction Description
CLKFX Output Multiplies the CLKIN frequency by
the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
CLKFX180 Output Generates a clock signal with the
same frequency as CLKFX, but
shifted 180° out-of-phase.
fCLKFX fCLKIN
CLKFX_MULTIPLY
CLKFX_DIVIDE
----------------------------------------------------


=
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 54
The CLKFX_DIVIDE is an integer ranging from 1 to 32,
inclusive and forms the denominator in Equation 1. For
example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3,
the frequency of the output clock signal is 5/3 that of the
input clock signal. These attributes and their acceptable
ranges are described in Table 34.
Any combination of integer values can be assigned to the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes,
provided that two conditions are met:
1. The two values fall within their corresponding ranges,
as specified in Table 34.
2. The fCLKFX output frequency calculated in Equation 1
falls within the DCM’s operating frequency
specifications (see Table 107 in Module 3).
DFS With or Without the DLL
Although the CLKIN input is shared with both units, the DFS
unit functions with or separately from the DLL unit. Separate
from the DLL, the DFS generates an output frequency from
the CLKIN frequency according to the respective
CLKFX_MULTIPLY and CLKFX_DIVIDE values. Frequency
synthesis does not require a feedback loop. Furthermore,
without the DLL, the DFS unit supports a broader operating
frequency range.
With the DLL, the DFS unit operates as described above,
only with the additional benefit of eliminating the clock
distribution delay. In this case, a feedback loop from the
CLK0 or CLK2X output to the CLKFB input must be present.
When operating with the DLL unit, the DFS’s CLKFX and
CLKFX180 outputs are phase-aligned with the CLKIN input
every CLKFX_DIVIDE cycles of CLKIN and every
CLKFX_MULTIPLY cycles of CLKFX. For example, when
CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input
and output clock edges coincide every three CLKIN input
periods, which is equivalent in time to five CLKFX output
periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values
result in faster lock times. Therefore, CLKFX_MULTIPLY
and CLKFX_DIVIDE must be factored to reduce their values
wherever possible. For example, given CLKFX_MULTIPLY
= 9 and CLKFX_DIVIDE = 6, removing a factor of three
yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2.
While both value-pairs result in the multiplication of clock
frequency by 3/2, the latter value-pair enables the DLL to
lock more quickly.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, eight of the nine DCM clock outputsCLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKFX, and
CLKFX180provide either quadrant or half-period phase
shifting of the input clock.
Second, the PS unit provides additional fine phase shift
control of all nine DCM outputs. The PS unit accomplishes
this by introducing a “fine phase shift” delay (TPS) between
the CLKFB and CLKIN signals inside the DLL unit. In FIXED
phase shift mode, the fine phase shift is specified at design
time with a resolution down to 1/256th of a CLKIN cycle or
one delay step (DCM_DELAY_STEP), whichever is greater.
This fine phase shift value is relative to the coarser quadrant
or half-period phase shift of the DCM clock output. When
used, the PS unit shifts the phase of all nine DCM clock
output signals.
Enabling Phase Shifting and Selecting an Operat-
ing Mode
The CLKOUT_PHASE_SHIFT attribute controls the PS unit
for the specific DCM instantiation. As described in Table 35,
this attribute has three possible values: NONE, FIXED, and
VARIABLE. When CLKOUT_PHASE_SHIFT = NONE, the
PS unit is disabled and the DCM output clocks are
phase-aligned to the CLKIN input via the CLKFB feedback
path. Figure 44a shows this case.
The PS unit is enabled when the CLKOUT_PHASE_SHIFT
attribute is set to FIXED or VARIABLE modes. These two
modes are described in the sections that follow.
Table 34: DFS Attributes
Attribute Description Values
CLKFX_MULTIPLY Frequency multiplier
constant
Integer from 2
to 32, inclusive
CLKFX_DIVIDE Frequency divisor
constant
Integer from 1
to 32, inclusive
Table 35: PS Attributes
Attribute Description Values
CLKOUT_PHASE_SHIFT Disables the PS component or chooses between Fixed
Phase and Variable Phase modes.
NONE, FIXED, VARIABLE
PHASE_SHIFT Determines size and direction of initial fine phase shift. Integers from –255 to +255
Spartan-3E FPGA Family: Functional Description
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Product Specification 55
FIXED Phase Shift Mode
The FIXED phase shift mode shifts the DCM outputs by a
fixed amount (TPS), controlled by the user-specified
PHASE_SHIFT attribute. The PHASE_SHIFT value (shown
as P in Figure 44) must be an integer ranging from –255 to
+255. PHASE_SHIFT specifies a phase shift delay as a
fraction of the TCLKIN. The phase shift behavior is different
between ISE 8.1, Service Pack 3 and prior software
versions, as described below.
Design Note
Prior to ISE 8.1i, Service Pack 3, the FIXED phase shift
feature operated differently than the Spartan-3 DCM design
primitive and simulation model. Designs using software
prior to ISE 8.1i, Service Pack 3 require recompilation using
the latest ISE software release. The following Answer
Record contains additional information:
http://www.xilinx.com/support/answers/23153.htm.
FIXED Phase Shift using ISE 8.1i, Service Pack 3 and
later: See Equation 2. The value corresponds to a phase
shift range of –360° to +360°, which matches behavior of
the Spartan-3 DCM design primitive and simulation model.
Eq 2
FIXED Phase Shift prior to ISE 8.1i, Service Pack 3: See
Equation 3. The value corresponds to a phase shift range of
–180° to +180° degrees, which is different from the
Spartan-3 DCM design primitive and simulation model.
Designs created prior to ISE 8.1i, Service Pack 3 must be
recompiled using the most recent ISE development
software.
Eq 3
When the PHASE_SHIFT value is zero, CLKFB and CLKIN
are in phase, the same as when the PS unit is disabled.
When the PHASE_SHIFT value is positive, the DCM
outputs are shifted later in time with respect to CLKIN input.
When the attribute value is negative, the DCM outputs are
shifted earlier in time with respect to CLKIN.
Figure 44b illustrates the relationship between CLKFB and
CLKIN in the Fixed Phase mode. In the Fixed Phase mode,
the PSEN, PSCLK, and PSINCDEC inputs are not used
and must be tied to GND.
Equation 2 or Equation 3 applies only to FIXED phase shift
mode. The VARIABLE phase shift mode operates
differently.
tPS
PHASESHIFT
256
----------------------------------------


TCLKIN
=
tPS
PHASESHIFT
512
----------------------------------------


TCLKIN
=
X-Ref Target - Figure 44
Figure 44: NONE and FIXED Phase Shifter Waveforms (ISE 8.1i, Service Pack 3 and later)
DS312-2_61_021606
CLKIN
CLKFB
* T
CLKIN
P
256
b. CLKOUT_PHASE_SHIFT = FIXED
Shift Range over all P Values: –255 +255
0
CLKIN
CLKFB
a. CLKOUT_PHASE_SHIFT = NONE
(via CLK0 or CLK2X feedback)
(via CLK0 or CLK2X feedback)
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 56
VARIABLE Phase Shift Mode
In VARIABLE phase shift mode, the FPGA application
dynamically adjusts the fine phase shift value using three
inputs to the PS unit (PSEN, PSCLK, and PSINCDEC), as
defined in Table 36 and shown in Figure 40.
The FPGA application uses the three PS inputs on the
Phase Shift unit to dynamically and incrementally increase
or decrease the phase shift amount on all nine DCM clock
outputs.
To adjust the current phase shift value, the PSEN enable
signal must be High to enable the PS unit. Coincidently,
PSINCDEC must be High to increment the current phase
shift amount or Low to decrement the current amount. All
VARIABLE phase shift operations are controlled by the
PSCLK input, which can be the CLKIN signal or any other
clock signal.
Design Note
The VARIABLE phase shift feature operates differently from
the Spartan-3 DCM; use the DCM_SP primitive, not the
DCM primitive.
DCM_DELAY_STEP
DCM_DELAY_STEP is the finest delay resolution available
in the PS unit. Its value is provided at the bottom of
Table 105 in Module 3. For each enabled PSCLK cycle that
PSINCDEC is High, the PS unit adds one DCM_
DELAY_STEP of phase shift to all nine DCM outputs.
Similarly, for each enabled PSCLK cycle that PSINCDEC is
Low, the PS unit subtracts one DCM_ DELAY_STEP of
phase shift from all nine DCM outputs.
Because each DCM_DELAY_STEP has a minimum and
maximum value, the actual phase shift delay for the present
phase increment/decrement value (VALUE) falls within the
minimum and maximum values according to Equation 4 and
Equation 5.
Eq 4
Eq 5
The maximum variable phase shift steps, MAX_STEPS, is
described in Equation 6 or Equation 7, for a given CLKIN
input period, TCLKIN, in nanoseconds. To convert this to a
phase shift range measured in time and not steps, use
MAX_STEPS derived in Equation 6 and Equation 7 for
VALUE in Equation 4 and Equation 5.
If CLKIN <60 MHz:
Eq 6
If CLKIN 60 MHz:
Eq 7
The phase adjustment might require as many as 100 CLKIN
cycles plus 3 PSCLK cycles to take effect, at which point the
DCM’s PSDONE output goes High for one PSCLK cycle.
This pulse indicates that the PS unit completed the previous
adjustment and is now ready for the next request.
Asserting the Reset (RST) input returns the phase shift to
zero.
Table 36: Signals for Variable Phase Mode
Signal Direction Description
PSEN(1) Input Enables the Phase Shift unit for variable phase adjustment.
PSCLK(1) Input Clock to synchronize phase shift adjustment.
PSINCDEC(1) Input When High, increments the current phase shift value. When Low, decrements the current
phase shift value. This signal is synchronized to the PSCLK signal.
PSDONE Output Goes High to indicate that the present phase adjustment is complete and PS unit is ready for
next phase adjustment request. This signal is synchronized to the PSCLK signal.
Notes:
1. This input supports either a true or inverted polarity.
TPS Max()VALUE DCM_DELAY_STEP_MAX=
TPS Min()VALUE DCM_DELAY_STEP_MIN=
MAX_STEPS INTEGER 10 TCLKIN 3()()[]±=
MAX_STEPS INTEGER 15 TCLKIN 3()()[]±=
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 57
Status Logic
The Status Logic indicates the present state of the DCM
and a means to reset the DCM to its initial known state. The
Status Logic signals are described in Table 37.
In general, the Reset (RST) input is only asserted upon
configuring the FPGA or when changing the CLKIN
frequency. The RST signal must be asserted for three or
more CLKIN cycles. A DCM reset does not affect attribute
values (for example, CLKFX_MULTIPLY and
CLKFX_DIVIDE). If not used, RST is tied to GND.
The eight bits of the STATUS bus are described in Table 38.
Stabilizing DCM Clocks Before User Mode
The STARTUP_WAIT attribute shown in Table 39 optionally
delays the end of the FPGA’s configuration process until
after the DCM locks to its incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all DCMs that have their
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream
generator (BitGen) option LCK_cycle specifies one of the
six cycles in the Startup phase. The selected cycle defines
the point at which configuration stalls until all the LOCKED
outputs go High. See Start-Up, page 106 for more
information.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
Table 37: Status Logic Signals
Signal Direction Description
RST Input A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of
zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0] Output The bit values on the STATUS bus provide information regarding the state of DLL and PS
operation
LOCKED Output Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are
out-of-phase when Low.
Table 38: DCM Status Bus
Bit Name Description
0 Reserved -
1 CLKIN Stopped When High, indicates that the CLKIN input signal is not toggling. When Low, indicates CLKIN is toggling.
This bit functions only when the CLKFB input is connected.(1)
2 CLKFX Stopped When High, indicates that the CLKFX output is not toggling. When Low, indicates the CLKFX output is
toggling. This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6 Reserved -
Notes:
1. When only the DFS clock outputs but none of the DLL clock outputs are used, this bit does not go High when the CLKIN signal stops.
Table 39: STARTUP_WAIT Attribute
Attribute Description Values
STARTUP_WAIT When TRUE, delays
transition from
configuration to user
mode until DCM
locks to the input
clock.
TRUE, FALSE
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 58
Clocking Infrastructure
For additional information, refer to the “Using Global Clock
Resources” chapter in UG331.
The Spartan-3E clocking infrastructure, shown in Figure 45,
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals
throughout the FPGA. The infrastructure also includes the
clock inputs and BUFGMUX clock buffers/multiplexers. The
Xilinx Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Clock Inputs
Clock pins accept external clock signals and connect
directly to DCMs and BUFGMUX elements. Each
Spartan-3E FPGA has:
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
Clock inputs optionally connect directly to DCMs using
dedicated connections. Table 30, Table 31, and Table 32
show the clock inputs that best feed a specific DCM within a
given Spartan-3E part number. Different Spartan-3E FPGA
densities have different numbers of DCMs. The
XC3S1200E and XC3S1600E are the only two densities
with the left- and right-edge DCMs.
Each clock input is also optionally a user-I/O pin and
connects to internal interconnect. Some clock pad pins are
input-only pins as indicated in Module 4, Pinout
Descriptions.
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a
multiplexer to switch between two unrelated, possibly
asynchronous clock signals (BUFGMUX).
Each BUFGMUX element, shown in Figure 46, is a 2-to-1
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 40. The switching from one clock to the
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock. The two clock inputs
can be asynchronous with regard to each other, and the S
input can change at any time, except for a short setup time
prior to the rising edge of the presently selected clock (I0 or
I1). This setup time is specified as TGSI in Table 101,
page 137. Violating this setup time requirement possibly
results in an undefined runt pulse output.
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in Figure 46. As shown in Figure 45, there are 24
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly
global and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in Figure 46. For
example, the input on I0 of one BUFGMUX is also a shared
input to I1 of the adjacent BUFGMUX.
The clock switch matrix for the left- and right-edge
BUFGMUX elements receive signals from any of the three
following sources: an LHCLK or RHCLK pin as appropriate,
a Double-Line interconnect, or a DCM in the XC3S1200E
and XC3S1600E devices.
Table 40: BUFGMUX Select Mechanism
S Input O Output
0 I0 Input
1 I1 Input
Spartan-3E FPGA Family: Functional Description
DS312 (v4.2) December 14, 2018 www.xilinx.com
Product Specification 59
X-Ref Target - Figure 45
Figure 45: Spartan-3E Internal Quadrant-Based Clock Network (Electrical Connectivity View)
8888
4
8
88
8
Left Spine
Top Left
Quadrant (TL)
Top Right
Quadrant (TR)
Bottom Right
Quadrant (BR)
Bottom Left
Quadrant (BL)
Right Spine
HorizontalSpine
Top Spine
Bottom Spine
4
DS312-2_04_041106
DCM
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S1200E (X1Y3)
XC3S1600E (X1Y3)
4
DCM
XC3S250E (X0Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
4
4 4
4
DCM
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
4
DCM
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
X1Y10 X1Y11 X2Y10 X2Y11
GCLK6GCLK7
GCLK10GCLK11
GCLK4GCLK5
GCLK8GCLK9
X1Y0 X1Y1 X2Y0 X2Y1
GCLK14GCLK15
GCLK2GCLK3
GCLK12GCLK13
GCLK0GCLK1
X0Y6 X0Y7 X0Y8X0Y9
LHCLK5LHCLK4 LHCLK7LHCLK6
X0Y2 X0Y3X0Y4 X0Y5
LHCLK1LHCLK0 LHCLK3LHCLK2
X3Y5 X3Y4 X3Y3X3Y2
RHCLK6RHCLK7 RHCLK4RHCLK5
X3Y9 X3Y8X3Y7 X3Y6
RHCLK2RHCLK3RHCLK0RHCLK1
2
2
2
2
2
2
DCM
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
2
2
DCM
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
DCM
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
DCM
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
Global Clock Inputs
Global Clock Inputs
Left-Half Clock Inputs
Right-Half Clock Inputs
BUFGMUX
BUFGMUX
H
G
B
A
D
C
F
E
A
C
H
G
B
A
D
C
F
E
B
D
E
GFH
pair Clock Line
in Quadrant
Note 4
Note 4
Note 3
Note 3
8 8
88
4
4
8
8
8
8
2
2
2
22
2
2
2
Notes:
1. The diagram presents electrical connectivity. The diagram locations do not necessarily match the physical location on the
device, although the coordinate locations shown are correct.
2. Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the
XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die.
3. See Figure 47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device.
4. See Figure 47b, which shows how the eight clock lines are multiplexed on the right-hand side of the device.
5. For best direct clock inputs to a particular clock buffer, not a DCM, see Table 41.
6. For best direct clock inputs to a particular DCM, not a BUFGMUX, see Table 30, Table 31, and Table 32. Direct pin inputs to a
DCM are shown in gray.
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Product Specification 60
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line
interconnect.
Table 41 indicates permissible connections between clock
inputs and BUFGMUX elements. The I0-input provides the
best input path to a clock buffer. The I1-input provides the
secondary input for the clock multiplexer function.
The four BUFGMUX elements on the top edge are paired
together and share inputs from the eight global clock inputs
along the top edge. Each BUFGMUX pair connects to four
of the eight global clock inputs, as shown in Figure 45. This
optionally allows differential inputs to the global clock inputs
without wasting a BUFGMUX element.
Table 41: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadran
t Clock
Line(1)
Left-Half BUFGMUX Top or Bottom BUFGMUX Right-Half BUFGMUX
Location(2) I0 Input I1 Input Location(2) I0 Input I1 Input Location(2) I0 Input I1 Input
HX0Y9 LHCLK7 LHCLK6 X1Y10 GCLK7 or
GCLK11
GCLK6 or
GCLK10 X3Y9 RHCLK3 RHCLK2
GX0Y8 LHCLK6 LHCLK7 X1Y11 GCLK6 or
GCLK10
GCLK7 or
GCLK11 X3Y8 RHCLK2 RHCLK3
FX0Y7 LHCLK5 LHCLK4 X2Y10 GCLK5 or
GCLK9
GCLK4 or
GCLK8 X3Y7 RHCLK1 RHCLK0
EX0Y6 LHCLK4 LHCLK5 X2Y11 GCLK4 or
GCLK8
GCLK5 or
GCLK9 X3Y6 RHCLK0 RHCLK1
DX0Y5 LHCLK3 LHCLK2 X1Y0 GCLK3 or
GCLK15
GCLK2 or
GCLK14 X3Y5 RHCLK7 RHCLK6
CX0Y4 LHCLK2 LHCLK3 X1Y1 GCLK2 or
GCLK14
GCLK3 or
GCLK15 X3Y4 RHCLK6 RHCLK7
BX0Y3 LHCLK1 LHCLK0 X2Y0 GCLK1 or
GCLK13
GCLK0 or
GCLK12 X3Y3 RHCLK5 RHCLK4
AX0Y2 LHCLK0 LHCLK1 X2Y1 GCLK0 or
GCLK12
GCLK1 or
GCLK13 X3Y2 RHCLK4 RHCLK5
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 45 for specific BUFGMUX locations, and Figure 47 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
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Product Specification 61
The connections for the bottom-edge BUFGMUX elements
are similar to the top-edge connections (see Figure 46).
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
Quadrant Clock Routing
The clock routing within the FPGA is quadrant-based, as
shown in Figure 45. Each clock quadrant supports eight
total clock signals, labeled ‘A’ through ‘H’ in Table 41 and
Figure 47. The clock source for an individual clock line
originates either from a global BUFGMUX element along
the top and bottom edges or from a BUFGMUX element
along the associated edge, as shown in Figure 47. The
clock lines feed the synchronous resource elements (CLBs,
IOBs, block RAM, multipliers, and DCMs) within the
quadrant.
The four quadrants of the device are:
Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement
constraints.
To estimate the quadrant location for a particular I/O, see
the footprint diagrams in Module 4, Pinout Descriptions. For
exact quadrant locations, use the floorplanning tool. In the
QFP packages (VQ100, TQ144 and PQ208) the quadrant
borders fall in the middle of each side of the package, at a
GND pin. The clock inputs fall on the quadrant boundaries,
as indicated in Table 42.
In a few cases, a dedicated input is physically in one
quadrant of the device but connects to a different clock
quadrant:
FT256, H16 is in clock quadrant BR
FG320, K2 is in clock quadrant BL
FG400, L8 is in clock quadrant TL and the I/O at N11 is
in clock quadrant BL
FG484, M2 is in clock quadrant TL and L15 is in clock
quadrant BR
X-Ref Target - Figure 46
Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity
BUFGMUX
LHCLK or
RHCLK input
Double Line
DCM output*
Left-/Right-Half BUFGMUX
CLK Switch
Matrix
S
O
O
S
I1
I0
I1
I0
BUFGMUX
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
S
O
O
S
I1
I0
I1
I0
1st GCLK pin
2nd GCLK pin
1st DCM output
2nd DCM output
Double Line
DS312-2_16_110706
0
1
0
1
0
1
0
1
*(XC3S1200E and
XC3S1600E only)
Table 42: QFP Package Clock Quadrant Locations
Clock Pins Quadrant
GCLK[3:0] BR
GCLK[7:4] TR
GCLK[11:8] TL
GCLK[15:12] BL
RHCLK[3:0] BR
RHCLK[7:4] TR
LHCLK[3:0] TL
LHCLK[7:4] BL
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Product Specification 62
The outputs of the top or bottom BUFGMUX elements
connect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 45. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
in a single clock quadrant. Figure 47 shows how the clock
lines in each quadrant are selected from associated
BUFGMUX sources. For example, if quadrant clock ‘A’ in
the bottom left (BL) quadrant originates from
BUFGMUX_X2Y1, then the clock signal from
BUFGMUX_X0Y2 is unavailable in the bottom left quadrant.
However, the top left (TL) quadrant clock ‘A’ can still solely
use the output from either BUFGMUX_X2Y1 or
BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock
network, the Xilinx development software automatically
disables all clock segments not in use.
X-Ref Target - Figure 47
Figure 47: Clock Sources for the Eight Clock Lines within a Clock Quadrant
D
X1Y0 (Global)
X0Y5 (Left Half) D
X1Y0 (Global)
X3Y5 (Right Half)
C
X1Y1 (Global)
X0Y4 (Left Half) C
X1Y1 (Global)
X3Y4 (Right Half)
B
X2Y0 (Global)
X0Y3 (Left Half) B
X2Y0 (Global)
X3Y3 (Right Half)
X2Y1 (Global) A
X0Y2 (Left Half)
X2Y1 (Global) A
X3Y2 (Right Half)
BUFGMUX Output Clock Line
E
X2Y11 (Global)
X0Y6 (Left Half) E
X2Y11 (Global)
X3Y6 (Right Half)
F
X2Y10 (Global)
X0Y7 (Left Half) F
X2Y10 (Global)
X3Y7 (Right Half)
G
X1Y11 (Global)
X0Y8 (Left Half) G
X1Y11 (Global)
X3Y8 (Right Half)
H
X1Y10 (Global)
X0Y9 (Left Half) H
X1Y10 (Global)
X3Y9 (Right Half)
BUFGMUX Output
DS312-2_17_103105
a. Left (TL and BL Quadrants) Half of Die b. Right (TR and BR Quadrants) Half of Die
Clock Line
Spartan-3E FPGA Family: Functional Description
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Product Specification 63
Interconnect
For additional information, refer to the “Using Interconnect
chapter in UG331.
Interconnect is the programmable network of signal
pathways between the inputs and outputs of functional
elements within the FPGA, such as IOBs, CLBs, DCMs, and
block RAM.
Overview
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are
identical to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
Switch Matrix
The switch matrix connects to the different kinds of
interconnects across the device. An interconnect tile, shown
in Figure 48, is defined as a single switch matrix connected
to a functional element, such as a CLB, IOB, or DCM. If a
functional element spans across multiple switch matrices
such as the block RAM or multipliers, then an interconnect
tile is defined by the number of switch matrices connected
to that functional element. A Spartan-3E device can be
represented as an array of interconnect tiles where
interconnect resources are for the channel between any two
adjacent interconnect tile rows or columns as shown in
Figure 49.
X-Ref Target - Figure 48
Figure 48: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
CLB
18Kb
Block
RAM
MULT
18 x 18
Switch
Matrix IOB
Switch
Matrix DCM
DS312_08_100110
X-Ref Target - Figure 49
Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA
Switch
Matrix IOB Switch
Matrix IOB Switch
Matrix IOB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB
IOB
CLB
CLB
CLB
CLB
Switch
Matrix
Switch
Matrix
DS312_09_100110
Spartan-3E FPGA Family: Functional Description
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Product Specification 64
The four types of general-purpose interconnect available in
each channel, shown in Figure 50, are described below.
Long Lines
Each set of 24 long line signals spans the die both
horizontally and vertically and connects to one out of every
six interconnect tiles. At any tile, four of the long lines drive
or receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given
interconnect tile. Double lines are more connections and
more flexibility, compared to long line and hex lines.
Horizontal and Vertical
Long Lines
(horizontal channel
shown as an example)
X-Ref Target - Figure 50
Horizontal and Vertical
Hex Lines
(horizontal channel
shown as an example)
Horizontal and Vertical
Double Lines
(horizontal channel
shown as an example)
Direct Connections
Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles
CLB CLB
CLB CLB
CLB CLB
66 666
CLB CLB
CLB CLB
DS312-2_10_022305
24
CLB CLB CLB CLB CLB CLBCLB
8
DS312-2_11_020905
CLB
8
CLB CLB
DS312-2_15_022305
CLBCLB CLB
CLBCLB CLB
CLBCLB CLB
DS312-2_12_020905
Spartan-3E FPGA Family: Functional Description
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Product Specification 65
Direct Connections
Direct connect lines route signals to neighboring tiles:
vertically, horizontally, and diagonally. These lines most
often drive a signal from a “source” tile to a double, hex, or
long line and conversely from the longer interconnect back
to a direct line accessing a “destination” tile.
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in Table 43. These signals are available to the FPGA
application via the STARTUP_SPARTAN3E primitive.
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted
automatically during the FPGA configuration process,
guaranteeing that the FPGA starts-up in a known state.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for Dynamically Loading Multiple
Configuration Images Using MultiBoot Option, page 92. The
CLK input is an alternate clock for configuration Start-Up,
page 106.
Table 43: Spartan-3E Global Logic Control Signals
Global Control
Input Description
GSR
Global Set/Reset: When High,
asynchronously places all registers and
flip-flops in their initial state (see Initialization,
page 32). Asserted automatically during the
FPGA configuration process (see Start-Up,
page 106).
GTS
Global Three-State: When High,
asynchronously forces all I/O pins to a
high-impedance state (Hi-Z, three-state).
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Product Specification 66
Configuration
For additional information on configuration, refer to UG332:
Spartan-3 Generation Configuration User Guide.
Differences from Spartan-3 FPGAs
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glueless
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this
configuration process uses a subset of the device pins,
some of which are dedicated to configuration; other pins are
merely borrowed and returned to the application as
general-purpose user I/Os after configuration completes.
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide