AD8510,12,13 Datasheet

Analog Devices Inc.

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Datasheet

Precision, Very Low Noise, Low Input Bias Current,
Wide Bandwidth JFET Operational Amplifiers
Date Sheet AD8510/AD8512/AD8513
Rev. K Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Fast settling time: 500 ns to 0.1%
Low offset voltage: 400 μV maximum
Low TCVOS: 1 μV/°C typical
Low input bias current: 25 pA typical at VS = ±15 V
Dual-supply operation: ±5 V to ±15 V
Low noise: 8 nV/√Hz typical at f = 1 kHz
Low distortion: 0.0005%
No phase reversal
Unity-gain stable
APPLICATIONS
Instrumentation
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Audio
PIN CONFIGURATIONS
AD8510
TOP VIEW
(Not to Scale)
NULL
–IN
+IN
V–
NC
V+
OUT
NULL
02729-003
NC = NO CONNECT
1
2
3
45
6
7
8
AD8510
TOP VIEW
(Not to Scale)
NULL
–IN
+IN
V–
NC
V+
OUT
NULL
02729-004
NC = NO CONNECT
1
2
3
45
6
7
8
Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix)
AD8512
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
02729-001
1
2
3
45
6
7
8
AD8512
TOP VIEW
(Not to Scale)
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
02729-002
1
2
3
45
6
7
8
Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix)
AD8513
TOP VIEW
(Not to Scale)
OUT A
1
–IN A
2
+IN A
3
V+
4
+IN B
5
OUT D
–IN D
+IN D
V–
+IN C
14
13
12
11
10
–IN B
6
OUT B
7
–IN C
OUT C
9
8
02729-005
AD8513
TOP VIEW
(Not to Scale)
OUT A
–IN A
+IN A
V+
+IN B
OUT D
–IN D
+IN D
V–
+IN C
–IN B
OUT B
–IN C
OUT C
0
2729-006
1
2
3
4
5
14
13
12
11
10
6
7
9
8
Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)
GENERAL DESCRIPTION
The AD8510/AD8512/AD8513 are single-, dual-, and quad-
precision JFET amplifiers that feature low offset voltage, input
bias current, input voltage noise, and input current noise.
The combination of low offsets, low noise, and very low input
bias currents makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. The combination of dc precision, low noise, and
fast settling time results in superior accuracy in medical
instruments, electronic measurement, and automated test
equipment. Unlike many competitive amplifiers, the AD8510/
AD8512/AD8513 maintain their fast settling performance even
with substantial capacitive loads. Unlike many older JFET
amplifiers, the AD8510/AD8512/AD8513 do not suffer from
output phase reversal when input voltages exceed the maximum
common-mode voltage range.
Fast slew rate and great stability with capacitive loads make the
AD8510/AD8512/AD8513 a perfect fit for high performance
filters. Low input bias currents, low offset, and low noise result
in a wide dynamic range of photodiode amplifier circuits. Low
noise and distortion, high output current, and excellent speed
make the AD8510/AD8512/AD8513 great choices for audio
applications.
The AD8510/AD8512 are both available in 8-lead narrow SOIC_N
and 8-lead MSOP packages. MSOP-packaged devices are only
available in tape and reel. The AD8513 is available in 14-lead
SOIC_N and TSSOP packages.
The AD8510/AD8512/AD8513 are specified over the −40°C to
+125°C extended industrial temperature range.
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Typical Performance Characteristics ............................................. 8
General Application Information ................................................. 14
Input Overvoltage Protection ................................................... 14
Output Phase Reversal ............................................................... 14
Total Harmonic Distortion (THD) + Noise .............................. 14
Total Noise Including Source Resistors ................................... 14
Settling Time ............................................................................... 15
Overload Recovery Time .......................................................... 15
Capacitive Load Drive ............................................................... 15
Open-Loop Gain and Phase Response .................................... 16
Precision Rectifiers ..................................................................... 17
I-V Conversion Applications .................................................... 18
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
12/2018—Rev. J to Rev. K
Change to 8-Lead SOIC_N (R) Parameter, Table 4 ..................... 7
6/2017—Rev. I to Rev. J
Changes to Figure 14 Caption ......................................................... 8
Deleted Figure 39; Renumbered Sequentially ............................ 12
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
2/2009—Rev. H to Rev. I
Changes to Figure 25 ...................................................................... 10
Changes to Ordering Guide .......................................................... 20
10/2007—Rev. G to Rev. H
Changes to Crosstalk Section ........................................................ 18
Added Figure 58 .............................................................................. 18
6/2007—Rev. F to Rev. G
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 1 and Table 2 ....................................................... 3
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
6/2006—Rev. E to Rev. F
Changes to Figure 23 ........................................................................ 9
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
6/2004—Rev. D to Rev. E
Changes to Format ............................................................. Universal
Changes to Specifications ................................................................. 3
Updated Outline Dimensions ....................................................... 19
10/2003—Rev. C to Rev. D
Added AD8513 Model ....................................................... Universal
Changes to Specifications ................................................................. 3
Added Figure 36 through Figure 40 ............................................. 10
Added Figure 55 and Figure 57 .................................................... 17
Changes to Ordering Guide .......................................................... 20
9/2003—Rev. B to Rev. C
Changes to Ordering Guide ............................................................ 4
Updated Figure 2 ............................................................................ 10
Changes to Input Overvoltage Protection Section .................... 10
Changes to Figure 10 and Figure 11............................................. 12
Changes to Photodiode Circuits Section .................................... 13
Changes to Figure 13 and Figure 14............................................. 13
Deleted Precision Current Monitoring Section ......................... 14
Updated Outline Dimensions ....................................................... 15
3/2003—Rev. A to Rev. B
Updated Figure 5 ............................................................................ 11
Updated Outline Dimensions ....................................................... 15
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 3 of 21
8/2002—Rev. 0 to Rev. A
Added AD8510 Model ....................................................... Universal
Added Pin Configurations ............................................................... 1
Changes to Specifications ................................................................. 2
Changes to Ordering Guide ............................................................. 4
Changes to TPC 2 and TPC 3 .......................................................... 5
Added TPC 10 and TPC 12 ............................................................. 6
Replaced TPC 20 ............................................................................... 8
Replaced TPC 27 ............................................................................... 9
Changes to General Application Information Section ............... 10
Changes to Figure 5 ......................................................................... 11
Changes to I-V Conversion Applications Section ...................... 13
Changes to Figure 13 and Figure 14 ............................................. 13
Changes to Figure 17 ...................................................................... 14
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 4 of 21
SPECIFICATIONS
At VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade)1 V
OS 0.08 0.4 mV
−40°C < TA < +125°C 0.8 mV
Offset Voltage (A Grade) VOS 0.1 0.9 mV
−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 21 75 pA
−40°C < TA < +85°C 0.7 nA
−40°C < TA < +125°C 7.5 nA
Input Offset Current IOS 5 50 pA
−40°C < TA < +85°C 0.3 nA
−40°C < TA < +125°C 0.5 nA
Input Capacitance
Differential 12.5 pF
Common Mode 11.5 pF
Input Voltage Range −2.0 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +2.5 V 86 100 dB
Large-Signal Voltage Gain AVO R
L = 2 kΩ, VO = −3 V to +3 V 65 107 V/mV
Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 0.9 5 μV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 μV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ 4.1 4.3 V
Output Voltage Low VOL RL = 10 kΩ, −40°C < TA < +125°C −4.9 −4.7 V
Output Voltage High VOH RL = 2 kΩ 3.9 4.2 V
Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C −4.9 −4.5 V
Output Voltage High VOH RL = 600 Ω 3.7 4.1 V
Output Voltage Low VOL RL = 600 Ω, −40°C < TA < +125°C −4.8 −4.2 V
Output Current IOUT ±40 ±54 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 130 dB
Supply Current/Amplifier ISY
AD8510/AD8512/AD8513 VO = 0 V 2.0 2.3 mA
AD8510/AD8512 −40°C < TA < +125°C 2.5 mA
AD8513 −40°C < TA < +125°C 2.75 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 20 V/μs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 4 V step, G = +1 0.4 μs
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin φM 44.5 Degrees
NOISE PERFORMANCE
Voltage Noise Density en f = 10 Hz 34 nV/√Hz
f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz
Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p
1 AD8510/AD8512 only.
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 5 of 21
ELECTRICAL CHARACTERISTICS
At VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade)1 VOS 0.08 0.4 mV
−40°C < TA < +125°C 0.8 mV
Offset Voltage (A Grade) VOS 0.1 1.0 mV
−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 25 80 pA
−40°C < TA < +85°C 0.7 nA
−40°C < TA < +125°C 10 nA
Input Offset Current IOS 6 75 pA
−40°C < TA < +85°C 0.3 nA
−40°C < TA < +125°C 0.5 nA
Input Capacitance
Differential 12.5 pF
Common Mode 11.5 pF
Input Voltage Range −13.5 +13.0 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 86 108 dB
Large-Signal Voltage Gain AVO RL = 2 kΩ, VCM = 0 V,
VO = −13.5 V to +13.5 V
115 196 V/mV
Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 1.0 5 μV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 μV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ +14.0 +14.2 V
Output Voltage Low VOL RL = 10 kΩ, −40°C < TA < +125°C −14.9 −14.6 V
Output Voltage High VOH RL = 2 kΩ +13.8 +14.1 V
Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C –14.8 −14.5 V
Output Voltage High VOH RL = 600 Ω +13.5 +13.9 V
R
L = 600 Ω, −40°C < TA < +125°C +11.4 V
Output Voltage Low VOL RL = 600 Ω −14.3 −13.8 V
R
L = 600 Ω, −40°C < TA < +125°C −12.1 V
Output Current IOUT ±70 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 dB
Supply Current/Amplifier ISY
AD8510/AD8512/AD8513 VO = 0 V 2.2 2.5 mA
AD8510/AD8512 −40°C < TA < +125°C 2.6 mA
AD8513 −40°C < TA < +125°C 3.0 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 20 V/μs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 10 V step, G = +1 0.5 μs
To 0.01%, 0 V to 10 V step, G = +1 0.9 μs
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin φM 52 Degrees
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 6 of 21
Parameter Symbol Conditions Min Typ Max Unit
NOISE PERFORMANCE
Voltage Noise Density en f = 10 Hz 34 nV/√Hz
f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz
Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p
1 AD8510/AD8512 only.
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 7 of 21
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Input Voltage ±VS
Output Short-Circuit Duration to GND Observe derating curves
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Electrostatic Discharge
(Human Body Model)
2000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4. Thermal Resistance
Package Type θJA1 θ
JC Unit
8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC_N (R) 120 43 °C/W
14-Lead SOIC_N (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W
1 θJA is specified for worst case conditions, that is, θJA is specified for device
soldered in circuit board for surface-mount packages.
ESD CAUTION
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 8 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (mV)
NUMBER OF AMPLIFIERS
–0.5
0
20
40
60
–0.4 –0.3
80
100
120
–0.2 –0.1 00.1 0.2 0.3 0.4 0.5
V
SY
= ±15V
T
A
= 25°C
02729-007
Figure 7. Input Offset Voltage Distribution
T
C
V
OS
(µV/°C)
NUMBER OF AMPLIFIERS
0
0
5
10
15
1
20
25
30
2 3 4 5 6
02729-008
V
SY
= ±15V
B GRADE
Figure 8. AD8510/AD8512 TCVOS Distribution
T
C
V
OS
(µV/°C)
NUMBER OF AMPLIFIERS
0
0
5
10
15
1
20
25
30
2 3 4 5 6
02729-009
V
SY
= ±15V
A GRADE
Figure 9. AD8510/AD8512 TCVOS Distribution
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
–40
1
10
100
1k
–25
10k
100k
–10 520 35 50 65 80 95 110 125
02729-010
V
SY
= ±5V, ±15V
Figure 10. Input Bias Current vs. Temperature
TEMPERATURE (°C)
INPUT OFFSET CURRENT (pA)
–40
0.1
1
10
100
–25
1000
–10 520 35 50 65 80 95 110 125
±15V
±5V
02729-011
Figure 11. Input Offset Current vs. Temperature
Figure 12. Input Bias Current vs. Supply Voltage
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 9 of 21
SUPPLY VOLTAGE (V+ – V–)
SUPPLY CURRENT PER AMPLIFIER (mA)
8
1.0
1.1
1.2
13
1.3
1.4
1.6
18 23 28 30
1.7
1.8
1.5
1.9
2.0 T
A
= 25°C
02729-013
Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
0
0
2
4
10
6
8
12
20 30 40 50
14
16
10
60 70 80
V
OL
V
OH
V
SY
= ±15V
V
SY
= ±5V
V
OH
V
OL
02729-039
Figure 14. Output Voltage vs. Load Current
TEMPERATURE (°C)
SUPPLY CURRENT PER AMPLIFIER (mA)
–40
1.00
1.25
1.50
1.75
–10
2.00
2.25
2.50
520 65 80 110–25 35 50 95 125
±15V
±5V
02729-015
Figure 15. AD8512 Supply Current per Amplifier vs. Temperature
SUPPLY VOLTAGE (V+ – V–)
SUPPLY CURRENT (mA)
8
1.0
1.2
1.4
13
1.6
1.8
2.2
18 23 28 33
2.4
2.6
2.0
2.8
T
A
= 25°C
02729-016
Figure 16. AD8510 Supply Current vs. Supply Voltage
FREQUENCY (Hz)
GAIN (dB)
10k
–30
–20
–10
100k
0
10
30
1M 10M 50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
PHASE (Degrees)
V
SY
= ±15V
R
L
= 2.5kΩ
C
SCOPE
= 20pF
Φ
M
= 52°
02729-017
Figure 17. Open-Loop Gain and Phase vs. Frequency
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
–40
1.00
1.25
1.50
1.75
–10
2.00
2.25
2.50
520 65 80 110–25 35 50 95 125
±15V
±5V
02729-018
Figure 18. AD8510 Supply Current vs. Temperature
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 10 of 21
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
1k
–30
–20
–10
10k
0
10
30
1M 10M 50M
40
50
20
60
70
100k
02729-019
V
SY
= ±15V, ±5V
A
V
= 100
A
V
= 1
A
V
= 10
Figure 19. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
CMRR (dB)
100 1k
0
40
10k 10M 100M
60
80
20
100
120
100k 1M
VSY = ±15V
02729-020
Figure 20. CMRR vs. Frequency
FREQUENCY (Hz)
PSRR (dB)
100 1k
0
40
10k 10M 100M
60
80
20
100
120
100k 1M
–20
–PSRR
+PSRR
V
SY
= ±5V, ±15V
02729-021
Figure 21. PSRR vs. Frequency
FREQUENCY (Hz)
OUTPUT IMPEDANCE ()
100 1k
0
90
10k 10M 100M
150
180
60
270
300
100k 1M
30
120
210
240
A
V
= 1
A
V
= 100
A
V
= 10
V
SY
= ±15V
V
IN
= 50mV
02729-022
Figure 22. Output Impedance vs. Frequency
FREQUENCY (Hz)
110 100 1k
1
1k
100
10
10k
VOLTAGE NOISE DENSITY (nV/ Hz)
V
SY
= ±5V TO ±15V
02729-023
Figure 23. Voltage Noise Density vs. Frequency
TIME (1s/DIV)
VOLTAGE (1µV/DIV)
V
SY
= ±15V
02729-024
Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 11 of 21
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV Hz)
01
0
105
2 7 9
175
70
245
280
35
35
140
210
46810
V
SY
= ±5V T
O ±15V
02729-025
Figure 25. Voltage Noise Density vs. Frequency
TIME (1µs/DIV)
VOLTAGE (5V/DIV)
V
SY
= ±15V
R
L
= 2kΩ
C
L
= 100pF
A
V
= 1
02729-026
Figure 26. Large-Signal Transient Response
TIME (100ns/DIV)
VOLTAGE (50mV/DIV)
02729-027
V
SY
= ±15V
R
L
= 2kΩ
C
L
= 100pF
A
V
= 1
Figure 27. Small-Signal Transient Response
LOAD CAPACITANCE (pF)
SMALL-SIGNAL OVERSHOOT (%)
1
0
10
20
10
30
40
60
100 1k 10k
70
50
80
90
VSY = ±15V
RL = 2kΩ
02729-028
+OS
–OS
Figure 28. Small-Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
10k
–10
0
100k
10
20
40
1M 10M 50M
50
30
60
70
–20
–30
PHASE (Degrees)
–45
45
90
180
225
135
270
315
–90
–135
0
V
SY
= ±5V
R
L
= 2.5kΩ
C
SCOPE
= 20pF
Φ
M
= 44.5°
02729-029
Figure 29. Open-Loop Gain and Phase vs. Frequency
FREQUENCY (Hz)
CMRR (dB)
100
40
1k
60
10k 10M 100M
100
80
120
20
0100k 1M
VSY = ±5V
02729-030
Figure 30. CMRR vs. Frequency
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 12 of 21
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
100
60
1k
90
10k 10M 100M
240
120
270
30
0100k 1M
150
180
210
300
02729-031
V
SY
= ±5V
V
IN
= 50mV
A
V
= 100
A
V
= 10
A
V
= 1
Figure 31. Output Impedance vs. Frequency
TIME (1s/DIV)
VOLTAGE (1µV/DIV)
02729-032
V
SY
= ±5V
Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise
TIME (1µs/DIV)
VOLTAGE (2V/DIV)
V
SY
= ±5V
R
L
= 2kΩ
C
L
= 100pF
A
V
= 1
02729-033
Figure 33. Large-Signal Transient Response
TIME (100ns/DIV)
VOLTAGE (50mV/DIV)
VSY = ±5V
RL = 2kΩ
CL = 100pF
AV = 1
02729-034
Figure 34. Small-Signal Transient Response
LOAD CAPACITANCE (pF)
SMALL-SIGNAL OVERSHOOT (%)
1
0
10
20
10
30
40
60
100 1k 10k
70
80
50
90
100 VSY = ±5V
RL = 2kΩ
02729-035
–OS
+OS
Figure 35. Small-Signal Overshoot vs. Load Capacitance
T
C
V
OS
(µV/°C)
NUMBER OF AMPLIFIERS
01
0
40
2 5 6
60
80
10
100
90
3 4
70
50
30
20
V
S
= ±15V
02729-036
Figure 36. AD8513 TCVOS Distribution
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 13 of 21
T
C
V
OS
(µV/°C)
NUMBER OF AMPLIFIERS
01
0
40
2 5 6
60
80
100
34
20
V
S
= ±5V
120
02729-037
Figure 37. AD8513 TCVOS Distribution
SUPPLY VOLTAGE (V+ – V–)
SUPPLY CURRENT PER AMPLIFIER (mA)
813
1.5
1.7
18 33
1.8
1.9
2.0
23 28
1.6
2.1
2.5
2.4
2.3
2.2
T
A
= 25°C
02729-038
Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage
0
0.5
1.0
1.5
2.0
2.5
3.0
SUPPLY CURRENT PER AMPLIFIER (mA)
TEMPERATURE (°C)
–40 –25 –10 520 35 50 65 80 95 110 125
02729-040
±15V
±5V
Figure 39. AD8513 Supply Current per Amplifier vs. Temperature
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 14 of 21
GENERAL APPLICATION INFORMATION
INPUT OVERVOLTAGE PROTECTION
The AD8510/AD8512/AD8513 have internal protective
circuitry that allows voltages as high as 0.7 V beyond the
supplies to be applied at the input of either terminal without
causing damage. For higher input voltages, a series resistor is
necessary to limit the input current. The resistor value can be
determined from the formula
mA5
S
S
IN
R
VV
With a very low offset current of <0.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 μV to the offset.
OUTPUT PHASE REVERSAL
Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of an amplifier exceeds the maximum common-mode
voltage.
Phase reversal can cause permanent damage to the device and
can result in system lockups. The AD8510/AD8512/AD8513 do
not exhibit phase reversal when input voltages are beyond the
supplies.
TIME (20µs/DIV)
02729-057
VOLTAGE (2V/DIV)
V
IN
V
OUT
V
SY
= ±5V
A
V
= 1
R
L
= 10k
Figure 40. No Phase Reversal
TOTAL HARMONIC DISTORTION (THD) + NOISE
The AD8510/AD8512/AD8513 have low THD and excellent gain
linearity, making these amplifiers great choices for precision
circuits with high closed-loop gain and for audio application
circuits. Figure 41 shows that the AD8510/AD8512/AD8513 have
approximately 0.0005% of total distortion when configured in
positive unity gain (the worst case) and driving a 100 kΩ load.
FREQUENCY (Hz)
DISTORTION (%)
02729-056
0.01
0.001
0.0001
20 100 1k 10k 20k
V
SY
= ±5V
R
L
= 100k
BW = 22kHz
Figure 41. THD + N vs. Frequency
TOTAL NOISE INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the
AD8510/AD8512/AD8513 make them the ideal amplifiers for
circuits with substantial input source resistance. Input offset
voltage increases by less than 15 nV per 500 Ω of source
resistance at room temperature. The total noise density of the
circuit is
SS
nn
nTOTAL kTRRiee 4
2
2
where:
en is the input voltage noise density of the devices.
in is the input current noise density of the devices.
RS is the source resistance at the noninverting terminal.
k is Boltzmanns constant (1.38 × 10–23 J/K).
T is the ambient temperature in Kelvin (T = 273 + °C).
For RS < 3.9 kΩ, en dominates and enTOTAL ≈ en. The current noise
of the AD8510/AD8512/AD8513 is so low that its total density
does not become a significant term unless RS is greater than
165 MΩ, an impractical value for most applications.
The total equivalent rms noise over a specific bandwidth is
expressed as
BWee nTOTALnTOTAL
where BW is the bandwidth in hertz.
Note that the previous analysis is valid for frequencies larger
than 150 Hz and assumes flat noise above 10 kHz. For lower
frequencies, flicker noise (1/f) must be considered.
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 15 of 21
SETTLING TIME
Settling time is the time it takes the output of the amplifier to
reach and remain within a percentage of its final value after a
pulse is applied at the input. The AD8510/AD8512/AD8513
settle to within 0.01% in less than 900 ns with a step of 0 V to
10 V in unity gain. This makes each of these devices an excellent
choice as a buffer at the output of DACs whose settling time is
typically less than 1 μs.
In addition to the fast settling time and fast slew rate, low offset
voltage drift and input offset current maintain the full accuracy
of 12-bit converters over the entire operating temperature range.
OVERLOAD RECOVERY TIME
Overload recovery, also known as overdrive recovery, is the
time it takes the output of an amplifier to recover to its linear
region from a saturated condition. This recovery time is par-
ticularly important in applications where the amplifier must
amplify small signals in the presence of large transient voltages.
Figure 42 shows the positive overload recovery of the AD8510/
AD8512/AD8513. The output recovers in approximately 200 ns
from a saturated condition.
0V
–15V
200mV
0V
OUTPUTINPUT
VOLTAGE
TIME (2µs/DIV)
V
SY
= ±15V
V
IN
= 200mV
A
V
= –100
R
L
= 10k
02729-053
Figure 42. Positive Overload Recovery
The negative overdrive recovery time shown in Figure 43 is less
than 200 ns.
In addition to the fast recovery time, the AD8510/AD8512/
AD8513 show excellent symmetry of the positive and negative
recovery times. This is an important feature for transient signal
rectification because the output signal is kept equally undistorted
throughout any given period.
TIME (2µs/DIV)
VOLTAGE
–200mV
0V
0V
+15V
02729-054
INPUT OUTPUT
V
SY
= ±15V
A
V
= –100
R
L
= 10k
Figure 43. Negative Overload Recovery
CAPACITIVE LOAD DRIVE
The AD8510/AD8512/AD8513 are unconditionally stable at all
gains in inverting and noninverting configurations. Each device
is capable of driving a capacitive load of up to 1000 pF without
oscillation in unity gain using the worst case configuration.
However, as with most amplifiers, driving larger capacitive
loads in a unity-gain configuration can cause excessive
overshoot and ringing, or even oscillation. A simple snubber
network significantly reduces the amount of overshoot and
ringing. The advantage of this configuration is that the output
swing of the amplifier is not reduced, because RS is outside the
feedback loop.
7
4
6
AD8510
200mV R
S
C
S
C
L
V
OUT
V+
V–
02729-055
2
3
Figure 44. Snubber Network Configuration
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 16 of 21
Figure 45 shows a scope plot of the output of the AD8510/AD8512/
AD8513 in response to a 400 mV pulse. The circuit is configured in
positive unity gain (worst case) with a load experience of 500 pF.
TIME (1µs/DIV)
VOLTAGE (200mV/DIV)
V
SY
= ±15V
C
L
= 500pF
R
L
=10k
02729-041
Figure 45. Capacitive Load Drive Without Snubber
When the snubber circuit is used, the overshoot is reduced from
55% to less than 3% with the same load capacitance. Ringing is
virtually eliminated, as shown in Figure 46.
TIME (1µs/DIV)
VOLTAGE (200mV/DIV)
V
SY
= ±15V
R
L
= 10k
C
L
= 500pF
R
S
= 100
C
S
= 1nF
02729-042
Figure 46. Capacitive Load with Snubber Network
Optimum values for RS and CS depend on the load capacitance
and input stray capacitance and are determined empirically.
Table 5 shows a few values that can be used as starting points.
Table 5. Optimum Values for Capacitive Loads
CLOAD RS (Ω) CS
500 pF 100 1 nF
2 nF 70 100 pF
5 nF 60 300 pF
OPEN-LOOP GAIN AND PHASE RESPONSE
In addition to their impressive low noise, low offset voltage, and
offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
and capacitive loads.
Compared with Competitor A (see Figure 48) under the same
conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/
AD8513 have more than 8 MHz of bandwidth and a phase margin
of more than 52°.
Competitor A, on the other hand, has only 4.5 MHz of band-
width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better
response than Competitor A, whose phase margin is degraded
to less than 0, indicating oscillation.
FREQUENCY (Hz)
GAIN (dB)
10k
–30
–20
–10
100k
0
10
30
1M 10M 50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
PHASE (Degrees)
02729-043
V
SY
= ±15V
R
L
= 2.5k
C
L
= 0pF
Figure 47. Frequency Response of the AD8510/AD8512/AD8513
FREQUENCY (Hz)
GAIN (dB)
10k
–30
–20
–10
100k
0
10
30
1M 10M 50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
PHASE (Degrees)
02729-044
V
SY
= ±15V
R
L
= 2.5k
C
L
= 0pF
Figure 48. Frequency Response of Competitor A
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 17 of 21
PRECISION RECTIFIERS
Rectifying circuits are used in a multitude of applications. One
of the most popular uses is in the design of regulated power
supplies, where a rectifier circuit is used to convert an input
sinusoid to a unipolar output voltage.
However, there are some potential problems with amplifiers
used in this manner. When the input voltage (VIN) is negative,
the output is zero, and the magnitude of VIN is doubled at the
inputs of the op amp. If this voltage exceeds the power supply
voltage, it can permanently damage some amplifiers. In addition,
the op amp must come out of saturation when VIN is negative.
This delays the output signal because the amplifier requires
time to enter its linear region.
Although the AD8510/AD8512/AD8513 have a very fast
overdrive recovery time, which makes them great choices for the
rectification of transient signals, the symmetry of the positive
and negative recovery times is also important to keep the output
signal undistorted.
Figure 49 shows the test circuit of the rectifier. The first stage of
the circuit is a half-wave rectifier. When the sine wave applied at
the input is positive, the output follows the input response.
During the negative cycle of the input, the output tries to swing
negative to follow the input, but the power supply restrains it to
zero. In a similar fashion, the second stage is a follower during
the positive cycle of the sine wave and an inverter during the
negative cycle.
8
4
2
1
3
1/2
AD8512
4
8
5
7
6
2/2
AD8512
R2
10k
R3
10k
R1
1k
OUT A
(HALF WAVE)
OUT B
(FULL WAVE)
10V
10V
V
IN
3V p-p
02729-045
Figure 49. Half-Wave and Full-Wave Rectifiers
TIME (1ms/DIV)
VOLTAGE (1V/DIV)
02729-046
Figure 50. Half-Wave Rectifier Signal (OUT A in Figure 49)
TIME (1ms/DIV)
VOLTAGE (1V/DIV)
02729-047
Figure 51. Full-Wave Rectifier Signal (OUT B in Figure 49)
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 18 of 21
I-V CONVERSION APPLICATIONS
Photodiode Circuits
Common applications for I-V conversion include photodiode
circuits where the amplifier is used to convert a current emitted
by a diode placed at the positive input terminal into an output
voltage.
The AD8510/AD8512/AD8513’s low input bias current, wide
bandwidth, and low noise make them each an excellent choice
for various photodiode applications, including fax machines,
fiber optic controls, motion sensors, and bar code readers.
The circuit shown in Figure 52 uses a silicon diode with zero
bias voltage. This is known as a photovoltaic mode; this
configuration limits the overall noise and is suitable for
instrumentation applications.
4
7
3
6
2
AD8510
Cf
R2
Rd Ct
V
EE
V
CC
02729-048
Figure 52. Equivalent Preamplifier Photodiode Circuit
A larger signal bandwidth can be attained at the expense of
additional output noise. The total input capacitance (Ct)
consists of the sum of the diode capacitance (typically 3 pF to
4 pF) and the amplifier’s input capacitance (12 pF), which
includes external parasitic capacitance. Ct creates a pole in the
frequency response that can lead to an unstable system. To
ensure stability and optimize the bandwidth of the signal, a
capacitor is placed in the feedback loop of the circuit shown in
Figure 52. It creates a zero and yields a bandwidth whose corner
frequency is 1/(2π(R2Cf)).
The value of R2 can be determined by the ratio
V/ID
where:
V is the desired output voltage of the op amp.
ID is the diode current.
For example, if ID is 100 μA and a 10 V output voltage is desired,
R2 can be 100 kΩ. Rd (see Figure 52) is a junction resistance
that drops typically by a factor of 2 for every 10°C increase in
temperature.
A typical value for Rd is 1000 MΩ. Because Rd >> R2, the
circuit behavior is not impacted by the effect of the junction
resistance. The maximum signal bandwidth is
CtR
ft
fMAX 22
where ft is the unity-gain frequency of the amplifier.
Cf can be calculated by
ftR
Ct
Cf 22
where ft is the unity-gain frequency of the op amp, and it achieves
a phase margin, φM, of approximately 45°.
A higher phase margin can be obtained by increasing the value
of Cf. Setting Cf to twice the previous value yields approximately
φM = 65° and a maximal flat frequency response, but it reduces the
maximum signal bandwidth by 50%.
Using the previous parameters with a Cf ≈ 1 pF, the signal
bandwidth is approximately 2.6 MHz.
Signal Transmission Applications
One popular signal transmission method uses pulse-width
modulation. High data rates can require a fast comparator
rather than an op amp. However, the need for sharp, undistorted
signals can favor using a linear amplifier.
The AD8510/AD8512/AD8513 make excellent voltage
comparators. In addition to a high slew rate, the AD8510/
AD8512/AD8513 have a very fast saturation recovery time. In
the absence of feedback, the amplifiers are in open-loop mode
(very high gain). In this mode of operation, they spend much of
their time in saturation.
The circuit shown in Figure 53 was used to compare two signals
of different frequencies, namely a 100 Hz sine wave and a 1 kHz
triangular wave. Figure 54 shows a scope plot of the resulting
output waveforms. A pull-up resistor (typically 5 kΩ) can be
connected from the output to VCC if the output voltage needs to
reach the positive rail. The trade-off is that power consumption
is higher.
V
OUT
V1
V2
4
2
6
7
3
–15V
+15
V
02729-049
Figure 53. Pulse-Width Modulator
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 19 of 21
TIME (2ms/DIV)
VOL
T
AGE (5V/DIV)
02729-050
Figure 54. Pulse-Width Modulation
Crosstalk
Crosstalk, also known as channel separation, is a measure of
signal feedthrough from one channel to another on the same
IC. The AD8512/AD8513 have a channel separation of better
than −90 dB for frequencies up to 10 kHz and of better than
−50 dB for frequencies up to 10 MHz. Figure 56 shows the
typical channel separation behavior between Amplifier A
(driving amplifier) and each of the following: Amplifier B,
Amplifier C, and Amplifier D.
V
OUT
1
2
7
6
5
4
3
8
+V
S
20k2.2k
5k5k
–V
S
V
IN
18V p-p
CROSSTALK = 20 log V
OUT
10V
IN
02729-052
Figure 55. Crosstalk Test Circuit
02729-051
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
100
–160 10k
–140
–120
–80
1k
–60
–20
–40
100k 1M 10M
–100
0
CH D CH C
CH B
Figure 56. Channel Separation
The AD8510 single has two additional active terminals that are
not present on the AD8512 dual or AD8513 quad devices. These
pins are labeled null and are used for fine adjustment of the
input offset voltage. Although the guaranteed maximum offset
voltage at room temperature is 400 µV and over the −40°C to
+125°C range is 800 mV maximum, this offset voltage can be
reduced by adding a potentiometer to the null pins as shown in
Figure 57. With the 20 k potentiometer shown, the adjustment
range is approximately ±3.5 mV. The potentiometer parallels
low value resistors in the drain circuit of the JFET differential
input pair and allows unbalancing of the drain currents to
change the offset voltage. If offset adjustment is not required,
these pins must be left unconnected.
Caution must be used when adding adjusting potentiometers to
any op amp with this capability for several reasons. First, there is
gain from these nodes to the output; therefore, capacitive coupling
from noisy traces to these nodes injects noise into the signal
path. Second, the temperature coefficient of the potentiometer
does not match the temperature coefficient of the internal resistors,
so the offset voltage drift with temperature is slightly affected.
Third, this provision is for adjusting the offset voltage of the
op amp, not for adjusting the offset of the overall system. Although
it is tempting to decrease the value of the potentiometer to attain
more range, this adversely affects the dc and ac parameters.
Instead, increase the potentiometer to 50 kΩ to decrease the
range if needed.
1
5
4
7
3
6
2
AD8510
INPUT OUTPUT
V+
V
OS
TRIM RANGE IS
TYPICALLY ±3.5mV
20k
V–
+
0
2729-058
Figure 57. Optional Offset Nulling Circuit
AD8510/AD8512/AD8513 Date Sheet
Rev. K | Page 20 of 21
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 58. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 59. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
4.50
4.40
4.30
14 8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
45°
Figure 61. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
Date Sheet AD8510/AD8512/AD8513
Rev. K | Page 21 of 21
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
AD8510ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B7A#
AD8510ARMZ −40°C to +125°C 8-Lead MSOP RM-8 B7A#
AD8510ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8510ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8510ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B8A#
AD8512ARMZ −40°C to +125°C 8-Lead MSOP RM-8 B8A#
AD8512ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8513ARZ −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARUZ −40°C to +125°C 14-Lead TSSOP RU-14
AD8513ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
©2002–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02729-0-12/18(K)

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